Block a user
fix (workaround) drtioaux packets being corrupted
Well then that didn't exactly work then, not sure why then. However in current situation writes and reads have to be aligned and 32 bit wide anyway, since separate bytes aren't addressable with this…
fix (workaround) drtioaux packets being corrupted
Because the fix seems like it's doing nothing in particular, I feel like it requires a bit of explanation.
Alright so: the implementation of the axi2csr bridge is alright - it does the job in…
77ca020450
drtio: fix garbage data on transmission
ad3aeb5109
fix (workaround) drtioaux packets being corrupted
433a9cdaf1
runtime: fix warnings on nondrtio systems
a79bef2243
runtime: provide/fix more libc mem functions
7b21889055
README: fix gateware build command
c1c56fbb79
up_destinations: fix warnings on non-drtio systems
c6ef9b117c
fix previous commit
dcfaf587ec
firmware: add UnwrapNoneError exception
a92561b9d3
implement rtio_get_destination_status (#177)
implement get_destination_status
fix (workaround) drtioaux packets being corrupted
Cache could make sense from what I read about them - with being involved in AXI transactions quite directly, for one. However... this is not the case.
I tried disabling L2 cache (well, not…
fix (workaround) drtioaux packets being corrupted
b1d0c1d8a2
fix (workaround) drtioaux packets being corrupted
dc54d5f9b6
update artiq/vivado
161044e78f
drop support for big-endian moninj
32f3c636c5
update artiq, work around annoying nix2.5 bug
50cafad18b
update artiq