mwojcik

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-19 14:22:29 +08:00

aa31a67f57 rtio_clocking: PLL requires a bit more time to lock

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-19 14:21:59 +08:00

0af337ff82 remove build warnings by adding "keep" and removing constraints

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-17 18:24:32 +08:00

4ea4073389 add fix_serdes_timing_path

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-17 18:23:04 +08:00

c14eda0580 rename clk signals, add "keep" attrs

mwojcik commented on pull request M-Labs/artiq-zynq#212

2023-01-16 18:25:21 +08:00

RTIO/SYS Clock merge

Turns out I can't really go without a bootstrap clock - standalone may work (although zc706 doesn't want to cooperate fully yet - maybe same power cycle issue?), but for DRTIO the transceivers…

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-16 18:15:39 +08:00

a5860f63f6 move clocking to zynq_clocking

10d857103d flake: update dependencies

881d0f795e test_dma: remove tsc mode

Compare 3 commits »

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-12 16:39:58 +08:00

9c7ca131ed zc706: fix TSC, PLL parameters

e79c04232f extract main clock signal from SYSCRG

c2ff32f5eb remove removed rtioclockmultiplier

4595f59ddc zc706: remove pll_reset

6190bbf8c9 test_dma: remove rtio cd

Compare 5 commits »

mwojcik created pull request M-Labs/artiq-zynq#212

2023-01-11 14:59:11 +08:00

[WIP] RTIO/SYS Clock merge

mwojcik pushed to rtiosys_clk_merge at mwojcik/artiq-zynq

2023-01-11 14:41:06 +08:00

fc927bbed2 zc706: change RTIO CRG to SYS

bd4a93e58d change init order, avoid providing bootstrap clock

18ed548301 rtio_clocking: remove unnecessary rtio_crg code

545a949048 kasli_soc: merge sys/rtio on standalone

d36899b485 firmware: unify RTIO error message format

Compare 10 commits »

mwojcik created branch rtiosys_clk_merge in mwojcik/artiq-zynq

2023-01-11 14:41:06 +08:00

mwojcik commented on issue M-Labs/artiq-zynq#205

2022-11-04 16:58:29 +08:00

Feature Request: EdgeCounters for NIST QC2 gateware

Sorry! I had this ready - but .bin files? or over 5mb files? are not allowed, giving no error - and I haven't noticed that it did not attach. Here's the zip.

mwojcik commented on issue M-Labs/artiq-zynq#205

2022-11-04 10:08:27 +08:00

Feature Request: EdgeCounters for NIST QC2 gateware

@ljstephenson - Try the attached compiled nist_qc2_master - let me know if you need any other variant.

mwojcik commented on issue M-Labs/artiq-zynq#205

2022-11-03 11:38:05 +08:00

Feature Request: EdgeCounters for NIST QC2 gateware

I'm not really sure how to add an entry to the local flake.nix to override this.

I would create a Vivado entry similar to the one in artiq, but with changed location, as a variable in the…

mwojcik commented on issue M-Labs/artiq-zynq#205

2022-11-03 10:38:16 +08:00

Feature Request: EdgeCounters for NIST QC2 gateware

I made the changes, and it does compile, but I'd like you to test them out first before they're merged into the master branch here.

https://git.m-labs.hk/mwojcik/artiq-zynq/src/branch/qc2_edge_c…

mwojcik pushed to qc2_edge_counters at mwojcik/artiq-zynq

2022-11-03 10:35:50 +08:00

1bb42bc048 qc2: add 4 edge counters to the end of rtio

d5402d899f flake: update dependencies

bbecead9a3 examples: fix ref_multiplier

c834e4f503 enable network and mgmt during Rust panic, make RTIO PLL lock failure a panic

Compare 4 commits »

mwojcik created branch qc2_edge_counters in mwojcik/artiq-zynq

2022-11-03 10:35:50 +08:00

mwojcik pushed to pll_error at mwojcik/artiq-zynq

2022-10-21 17:20:52 +08:00

c6d173a5c5 cleanup, reword comment

d080c65519 fix warnings, give empty section if nothing found

93bd98f6c0 better way of handling incorrect pc address

31ceee7e22 backtracing should be safe now

4034be5da8 check core before looking for kernel image

Compare 18 commits »

mwojcik pushed to pll_error at mwojcik/artiq-zynq

2022-10-21 17:18:53 +08:00

7323c1508a cleanup, reword comment

mwojcik created pull request M-Labs/artiq-zynq#203

2022-10-21 12:21:51 +08:00

kasli_soc: ident = variant name

mwojcik pushed to ident_variant at mwojcik/artiq-zynq

2022-10-21 12:08:19 +08:00

dc862a9051 match ident message with mainline