forked from M-Labs/zynq-rs
add Kasli-SoC POR control program
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kasli_soc_por.py
Normal file
17
kasli_soc_por.py
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from time import sleep
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from pyftdi.ftdi import Ftdi
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POR = 1 << 7
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def main():
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dev = Ftdi()
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dev.open_bitbang_from_url("ftdi://ftdi:4232h/0")
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dev.set_bitmode(POR, Ftdi.BitMode.BITBANG)
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dev.write_data(bytes([0]))
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sleep(0.1)
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dev.write_data(bytes([POR]))
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sleep(0.1)
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dev.close()
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if __name__ == "__main__":
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main()
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