forked from M-Labs/urukul-pld
remove duplicate platform
This commit is contained in:
169
ice40/xc2c.py
169
ice40/xc2c.py
@@ -1,169 +0,0 @@
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from migen.build.generic_platform import *
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from migen.build.xilinx import XilinxPlatform
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from migen.build.xilinx.ise import XilinxISEToolchain
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_io = [
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("tp", 0, Pins("A4")),
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("tp", 1, Pins("A5")),
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("tp", 2, Pins("B5")),
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("tp", 3, Pins("A6")),
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("tp", 4, Pins("A7")),
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("ifc_mode", 0, Pins("E14 B16 A16 B15")),
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("hw_rev", 0, Pins("C16 D15 E15 E16")),
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# 10k low: AD9912, 0R high: AD9910
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("variant", 0, Pins("A15")),
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# fail save LVDS enable, LVDS mode selection
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# high: type 2 receiver, failsafe low
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("fsen", 0, Pins("N15")),
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("clk", 0,
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Subsignal("div", Pins("E5")),
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Subsignal("in_sel", Pins("G5")),
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Subsignal("mmcx_osc_sel", Pins("C11")),
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Subsignal("osc_en_n", Pins("B6"))),
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("dds_common", 0,
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Subsignal("master_reset", Pins("F16")),
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Subsignal("io_reset", Pins("B9"))),
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("dds_sync", 0,
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Subsignal("clk0", Pins("P5"), Misc("PULLUP")), # DDS_SYNC_CLK0
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Subsignal("clk_out_en", Pins("T5")), # DDS_SYNC_CLK_OUTEN
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Subsignal("sync_sel", Pins("T10")), # DDS_SYNC_CLKSEL
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Subsignal("sync_out_en", Pins("R6"))), # DDS_SYNC_OUTEN
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("att", 0,
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Subsignal("clk", Pins("E9")),
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Subsignal("rst_n", Pins("N9")),
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Subsignal("le", Pins("E10 P8 C8 K4")),
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Subsignal("s_in", Pins("B7 D8 D7 L5")),
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Subsignal("s_out", Pins("C10 C9 E8 R9"))),
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("dds", 0,
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Subsignal("rf_sw", Pins("D13")),
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Subsignal("led", Pins("E11 B10")),
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Subsignal("smp_err", Pins("D4"), Misc("PULLUP")),
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Subsignal("pll_lock", Pins("E4"), Misc("PULLUP")),
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Subsignal("io_update", Pins("B1")),
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Subsignal("profile", Pins("A9 B8 A8")),
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Subsignal("osk", Pins("C13")),
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Subsignal("drover", Pins("D11")),
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Subsignal("drhold", Pins("E13")),
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Subsignal("drctl", Pins("C14")),
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Subsignal("reset", Pins("B13")),
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Subsignal("sck", Pins("A2")),
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Subsignal("sdo", Pins("A3"), Misc("PULLUP")),
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Subsignal("sdi", Pins("B2")),
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Subsignal("cs_n", Pins("B3"))),
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("dds", 1,
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Subsignal("rf_sw", Pins("C12")),
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Subsignal("led", Pins("A13 A11")),
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Subsignal("smp_err", Pins("J1"), Misc("PULLUP")),
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Subsignal("pll_lock", Pins("K2"), Misc("PULLUP")),
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Subsignal("io_update", Pins("P4")),
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Subsignal("profile", Pins("D3 D2 E2")),
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Subsignal("osk", Pins("C3")),
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Subsignal("drover", Pins("B4")),
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Subsignal("drhold", Pins("C7")),
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Subsignal("drctl", Pins("C4")),
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Subsignal("reset", Pins("F2")),
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Subsignal("sck", Pins("K3")),
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Subsignal("sdo", Pins("J3"), Misc("PULLUP")),
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Subsignal("sdi", Pins("K5")),
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Subsignal("cs_n", Pins("J4"))),
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("dds", 2,
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Subsignal("rf_sw", Pins("D10")),
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Subsignal("led", Pins("A14 B14")),
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Subsignal("smp_err", Pins("P6"), Misc("PULLUP")),
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Subsignal("pll_lock", Pins("N7"), Misc("PULLUP")),
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Subsignal("io_update", Pins("H5")),
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Subsignal("profile", Pins("M1 M6 M5")),
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Subsignal("osk", Pins("L1")),
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Subsignal("drover", Pins("L2")),
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Subsignal("drhold", Pins("L4")),
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Subsignal("drctl", Pins("K1")),
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Subsignal("reset", Pins("R10")),
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Subsignal("sck", Pins("H4")),
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Subsignal("sdo", Pins("J2"), Misc("PULLUP")),
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Subsignal("sdi", Pins("H3")),
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Subsignal("cs_n", Pins("H1"))),
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("dds", 3,
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Subsignal("rf_sw", Pins("D9")),
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Subsignal("led", Pins("A12 B11")),
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Subsignal("smp_err", Pins("N6"), Misc("PULLUP")),
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Subsignal("pll_lock", Pins("P7"), Misc("PULLUP")),
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Subsignal("io_update", Pins("E3")),
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Subsignal("profile", Pins("N3 P1 P2")),
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Subsignal("osk", Pins("N2")),
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Subsignal("drover", Pins("N5")),
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Subsignal("drhold", Pins("N4")),
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Subsignal("drctl", Pins("N1")),
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Subsignal("reset", Pins("T8")),
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Subsignal("sck", Pins("H2")),
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Subsignal("sdo", Pins("G3"), Misc("PULLUP")),
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Subsignal("sdi", Pins("F5")),
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Subsignal("cs_n", Pins("G4"))),
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("eem", 0,
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Subsignal("io", Pins("M2" )),
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Subsignal("oe", Pins("P15"))),
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("eem", 1,
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Subsignal("io", Pins("R13")),
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Subsignal("oe", Pins("M15"))),
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("eem", 2,
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Subsignal("io", Pins("T16")),
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Subsignal("oe", Pins("K15"))),
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("eem", 3,
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Subsignal("io", Pins("R16")),
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Subsignal("oe", Pins("N16"))),
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("eem", 4,
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Subsignal("io", Pins("R15")),
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Subsignal("oe", Pins("L15"))),
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("eem", 5,
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Subsignal("io", Pins("R14")),
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Subsignal("oe", Pins("M16"))),
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("eem", 6,
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Subsignal("io", Pins("R12")),
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Subsignal("oe", Pins("L16"))),
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("eem", 7,
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Subsignal("io", Pins("T15")),
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Subsignal("oe", Pins("P16"))),
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("eem", 8,
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Subsignal("io", Pins("M3")),
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Subsignal("oe", Pins("R7"))),
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("eem", 9,
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Subsignal("io", Pins("J5")),
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Subsignal("oe", Pins("T4"))),
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("eem", 10,
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Subsignal("io", Pins("R3")),
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Subsignal("oe", Pins("R4"))),
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("eem", 11,
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Subsignal("io", Pins("R2")),
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Subsignal("oe", Pins("R5"))),
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("eem", 12,
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Subsignal("io", Pins("R1")),
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Subsignal("oe", Pins("M7"))),
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("eem", 13,
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Subsignal("io", Pins("T1")),
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Subsignal("oe", Pins("R8"))),
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("eem", 14,
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Subsignal("io", Pins("T2")),
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Subsignal("oe", Pins("T7"))),
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("eem", 15,
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Subsignal("io", Pins("T3")),
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Subsignal("oe", Pins("M8"))),
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]
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "xc2c256-6-ft256", _io)
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self.toolchain.xst_opt = "-ifmt MIXED"
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self.toolchain.par_opt = ("-optimize speed -unused pullup "
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"-iostd LVCMOS33")
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