From 82dba2bb67990fa8a0c03af9b4f4621bde6b6332 Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Fri, 20 Mar 2020 00:45:10 +0100
Subject: [PATCH] ad7172: work on adc setup

---
 src/ad7172/adc.rs  | 14 +++++++++-----
 src/ad7172/regs.rs | 12 +++++++++++-
 src/main.rs        |  2 ++
 3 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/src/ad7172/adc.rs b/src/ad7172/adc.rs
index 0f684c0..edd308b 100644
--- a/src/ad7172/adc.rs
+++ b/src/ad7172/adc.rs
@@ -5,7 +5,7 @@ use log::info;
 use super::checksum::{ChecksumMode, Checksum};
 use super::AdcError;
 use super::{
-    regs, regs::RegisterData,
+    regs::{self, Register, RegisterData},
     Input, RefSource, PostFilter, DigitalFilterOrder,
 };
 
@@ -40,6 +40,10 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
         }
         info!("ADC id: {:04X} ({} retries)", adc_id, retries);
 
+        let mut adc_mode = <regs::AdcMode as Register>::Data::empty();
+        adc_mode.set_ref_en(true);
+        adc.write_reg(&regs::AdcMode, &mut adc_mode);
+
         Ok(adc)
     }
 
@@ -74,16 +78,16 @@ impl<SPI: Transfer<u8, Error = E>, NSS: OutputPin, E: fmt::Debug> Adc<SPI, NSS>
             data.set_refbuf_neg(true);
             data.set_ainbuf_pos(true);
             data.set_ainbuf_neg(true);
-            data.set_ref_sel(RefSource::External);
+            data.set_ref_sel(RefSource::Internal);
         })?;
         self.update_reg(&regs::FiltCon { index }, |data| {
             data.set_enh_filt_en(true);
             data.set_enh_filt(PostFilter::F16SPS);
             data.set_order(DigitalFilterOrder::Sinc5Sinc1);
         })?;
-        // let mut offset = <regs::Offset as regs::Register>::Data::empty();
-        // offset.set_offset(0);
-        // self.write_reg(&regs::Offset { index }, &mut offset);
+        let mut offset = <regs::Offset as regs::Register>::Data::empty();
+        offset.set_offset(0);
+        self.write_reg(&regs::Offset { index }, &mut offset);
         self.update_reg(&regs::Channel { index }, |data| {
             data.set_setup(index);
             data.set_enabled(true);
diff --git a/src/ad7172/regs.rs b/src/ad7172/regs.rs
index 25d2aaa..b0f989f 100644
--- a/src/ad7172/regs.rs
+++ b/src/ad7172/regs.rs
@@ -150,7 +150,17 @@ impl status::Data {
     reg_bits!(channel, 0, 0..=1, "Channel for which data is ready");
     reg_bit!(adc_error, 0, 6, "ADC error");
     reg_bit!(crc_error, 0, 5, "SPI CRC error");
-    reg_bit!(reg_error, 0,4, "Register error");
+    reg_bit!(reg_error, 0, 4, "Register error");
+}
+
+def_reg!(AdcMode, adc_mode, 0x01, 2);
+impl adc_mode::Data {
+    reg_bits!(clockset, set_clocksel, 1, 2..3, "Clock source");
+    reg_bits!(mode, set_mode, 1, 4..6, "Operating mode");
+    reg_bits!(delay, set_delay, 0, 0..2, "Delay after channel switch");
+    reg_bit!(sing_cyc, set_sing_cyc, 1, 5, "Can only used with single channel");
+    reg_bit!(hide_delay, set_hide_delay, 1, 6, "Hide delay");
+    reg_bit!(ref_en, set_ref_en, 0, 7, "Enable internal reference, output buffered 2.5 V to REFOUT");
 }
 
 def_reg!(IfMode, if_mode, 0x02, 2);
diff --git a/src/main.rs b/src/main.rs
index 7b19187..741b41c 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -92,6 +92,8 @@ fn main() -> ! {
     );
 
     let mut adc = ad7172::Adc::new(pins.adc_spi, pins.adc_nss).unwrap();
+    adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
+    adc.setup_channel(1, ad7172::Input::Ain2, ad7172::Input::Ain3).unwrap();
     let mut dac0 = ad5680::Dac::new(pins.dac0_spi, pins.dac0_sync);
     dac0.set(0).unwrap();
     let mut dac1 = ad5680::Dac::new(pins.dac1_spi, pins.dac1_sync);