mwojcik/nix-scripts
1
0
Fork 0
forked from M-Labs/nix-scripts
Code Issues Pull Requests Projects Releases Wiki Activity

mirny: update latest release to 0.3.1

Browse Source
This commit is contained in:
mwojcik 2024-09-25 11:49:56 +08:00
parent c7cafe6e61
commit b332d72c5e
2 changed files with 2 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
gluelogic/default.nix
View File

@ -58,12 +58,12 @@ in
src = <mirnySrc>;
};
mirny-cpld-release = buildMirnyCpld rec {
version = "0.3";
version = "0.3.1";
src = pkgs.fetchFromGitHub {
owner = "quartiq";
repo = "mirny";
rev = "v${version}";
sha256 = "sha256-u1iXcbGX6JkVgfpnCbkyTOVoMYnYcSufLBb6OBAeu8c=";
sha256 = "sha256-FbPUgXcUByEnczbnDCh8wYPO+rpSZSAabG1rtvA7mIs=";
};
};
mirny-cpld-legacy-almazny = buildMirnyCpld rec {
@ -76,16 +76,6 @@ in
};
patchPhase = "patch -p1 < ${./mirny-legacy-almazny.diff}";
};
mirny-cpld-almazny = buildMirnyCpld rec {
version = "0.3";
src = pkgs.fetchFromGitHub {
owner = "quartiq";
repo = "mirny";
rev = "v${version}";
sha256 = "sha256-u1iXcbGX6JkVgfpnCbkyTOVoMYnYcSufLBb6OBAeu8c=";
};
patchPhase = "patch -p1 < ${./mirny-almazny.diff}";
};
fastino-fpga = pkgs.stdenv.mkDerivation {
name = "fastino-fpga";
src = <fastinoSrc>;

40
gluelogic/mirny-almazny.diff
View File

@ -1,40 +0,0 @@
diff --git a/mirny.py b/mirny.py
index 6c041de..73991b1 100644
--- a/mirny.py
+++ b/mirny.py
@@ -135,7 +135,7 @@ class SR(Module):
)
]
- def connect_ext(self, ext, adr, mask):
+ def connect_ext(self, ext, adr, mask, sdi_passthrough=False):
adr &= mask
self._check_intersection(adr, mask)
self._slaves.append((ext, adr, mask))
@@ -146,12 +146,16 @@ class SR(Module):
stb.ce.eq(self.bus.re),
# don't glitch with &stb.o
ext.sck.eq(self.ext.sck),
- ext.sdi.eq(self.ext.sdi & stb.o),
ext.cs.eq(stb.o),
If(stb.o,
self.ext.sdo.eq(ext.sdo),
),
]
+ # Almazny shares one SDI with 4 devices, it cannot be masked by stb
+ if sdi_passthrough:
+ self.comb += ext.sdi.eq(self.ext.sdi)
+ else:
+ self.comb += ext.sdi.eq(self.ext.sdi & stb.o),
def intersection(a, b):
@@ -360,7 +364,7 @@ class Mirny(Module):
]
ext = Record(ext_layout)
- self.sr.connect_ext(ext, adr=i + 12, mask=mask)
+ self.sr.connect_ext(ext, adr=i + 12, mask=mask, sdi_passthrough=True)
self.comb += [
mezz[i + 3].oe.eq(1),
mezz[i + 3].o.eq(~ext.cs), # Almazny REG_LATCH