forked from M-Labs/nix-scripts
314 lines
10 KiB
Diff
314 lines
10 KiB
Diff
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diff --git a/Makefile b/Makefile
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index 667b8e7..ed97303 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -8,9 +8,15 @@ test:
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.PHONY: build
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build: build/mirny.vm6
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+.PHONY: legacy_almazny
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+legacy_almazny: build/mirny_legacy_almazny.vm6
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+
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build/mirny.vm6: mirny.py mirny_cpld.py
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python mirny_impl.py
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+build/mirny_legacy_almazny.vm6: mirny.py mirny_cpld.py
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+ python mirny_impl.py --legacy-almazny
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+
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REV:=$(shell git describe --always --abbrev=8 --dirty)
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.PHONY: release
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diff --git a/README.md b/README.md
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index 1bea35a..5e93809 100644
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--- a/README.md
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+++ b/README.md
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@@ -1,23 +1,39 @@
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-# Mirny CPLD code
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+# Mirny CPLD gateware
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-[Mirny overview](https://github.com/sinara-hw/mirny/wiki)
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+## Hardware
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+
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+[](https://github.com/sinara-hw/mirny/wiki)
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[Mirny Schematics](https://github.com/sinara-hw/mirny/releases)
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## Building
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-Needs migen and ISE.
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+Needs [migen](https://github.com/m-labs/migen) and [Xilinx ISE](https://www.xilinx.com/products/design-tools/ise-design-suite.html). Assumes ISE is installed in ``/opt/Xilinx``.
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```
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make
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-# and then look at/use flash.sh or make flash
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-
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-# or use fxload and xc3sprog:
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-/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum` && sleep 10 && \
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-xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
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-# look for "Verify: Success"
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```
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+## Flashing
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+
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+With Digilent [JTAG HS2](https://store.digilentinc.com/jtag-hs2-programming-cable/) cable:
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+
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+ - download firmware to dongle. Manually (adjust USB bus as needed):
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+ ```
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+ /sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-3/devnum`
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+ ```
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+ or automatically via the ``udev`` rule:
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+ ```
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+ SUBSYSTEM=="usb", ACTION="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", ATTR{manufacturer}=="Digilent", RUN+="/usr/bin/fxload -v -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D $tempnode"
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+ ```
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+
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+ - install [xc3sprog](http://xc3sprog.sourceforge.net/)
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+
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+ - ``flash_xc3.sh jtaghs2``
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+
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+ - look for ``Verify: Success``
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+
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+
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# License
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GPLv3+
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diff --git a/flash_xc3.sh b/flash_xc3.sh
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index 4c8a94c..c84b4d6 100755
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--- a/flash_xc3.sh
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+++ b/flash_xc3.sh
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@@ -1,8 +1,9 @@
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#!/bin/bash
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set -e
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-set -x
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-/sbin/fxload -t fx2 -I /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xusb_xp2.hex -D /dev/bus/usb/001/*`cat /sys/bus/usb/devices/1-7/devnum`
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-sleep 7
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-../xc3sprog/build/xc3sprog -c xpc -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
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+XC3SPROG=xc3sprog
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+CABLE=${1-xpc}
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+
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+set -x
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+$XC3SPROG -c $CABLE -m /opt/Xilinx/14.7/ISE_DS/ISE/xbr/data -v build/mirny.jed:w
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diff --git a/mirny.py b/mirny.py
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index 82edca2..6dc2612 100644
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--- a/mirny.py
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+++ b/mirny.py
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@@ -153,7 +153,6 @@ class SR(Module):
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),
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]
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-
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def intersection(a, b):
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(aa, am), (ba, bm) = a, b
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# TODO
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@@ -182,26 +181,26 @@ class Mirny(Module):
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SPI
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---
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- SPI xfer is ADR(7), WE(1), DAT(REG: 16, ATT: 8, PLL: 32)
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-
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- | ADR | TARGET |
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- |--------+--------|
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- | 0 | REG0 |
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- | 1 | REG1 |
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- | 2 | REG2 |
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- | 3 | REG3 |
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- | 4 | PLL0 |
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- | 5 | PLL1 |
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- | 6 | PLL2 |
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- | 7 | PLL3 |
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- | 8 | ATT0 |
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- | 9 | ATT1 |
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- | a | ATT2 |
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- | b | ATT3 |
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- | c | reserved |
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- | d | reserved |
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- | e | reserved |
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- | f | reserved |
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+ SPI xfer is ADR(7), WE(1), DAT(REG: 16, ATT: 8, PLL: 32, SR: 8)
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+
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+ | ADR | TARGET |
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+ |-----+----------------------|
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+ | 0 | REG0 |
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+ | 1 | REG1 |
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+ | 2 | REG2 |
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+ | 3 | REG3 |
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+ | 4 | PLL0 |
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+ | 5 | PLL1 |
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+ | 6 | PLL2 |
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+ | 7 | PLL3 |
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+ | 8 | ATT0 |
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+ | 9 | ATT1 |
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+ | a | ATT2 |
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+ | b | ATT3 |
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+ | c | (Legacy Almazny) SR1 |
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+ | d | (Legacy Almazny) SR2 |
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+ | e | (Legacy Almazny) SR3 |
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+ | f | (Legacy Almazny) SR4 |
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The SPI interface is CPOL=0, CPHA=0, SPI mode 0, 4-wire, full fuplex.
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@@ -223,8 +222,8 @@ class Mirny(Module):
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| Name | Width | Function |
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|-----------+-------+------------------------------------|
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| CE_N | 4 | PLL chip enable (bar) |
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- | CLK_SEL | 2 | Selects CLK source: 0 OSC, 1 MMCX, |
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- | | | 2 reserved, 3 SMA |
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+ | CLK_SEL | 2 | Selects CLK source: |
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+ | | | 0 OSC, 1 reserved, 2 MMCX, 3 SMA |
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| DIV | 2 | Clock divider configuration: |
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| | | 0: divide-by-one, |
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| | | 1: reserved, |
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@@ -234,6 +233,7 @@ class Mirny(Module):
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| FSEN_N | 1 | LVDS fail safe, Type 2 (bar) |
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| MUXOUT_EEM| 1 | route MUXOUT to EEM[4:8] |
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| EEM_MEZZIO| 1 | route EEM[4:8] to MEZZ_IO[0:4] |
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+ | ALMAZNY_OE| 1 | Almazny OE in legacy Almazny mode |
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| Name | Width | Function |
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|-----------+-------+------------------------------------|
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@@ -250,7 +250,7 @@ class Mirny(Module):
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The test points expose miscellaneous signals for debugging and are not part
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of the protocol revision.
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"""
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- def __init__(self, platform):
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+ def __init__(self, platform, legacy_almazny=False):
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self.eem = eem = []
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for i in range(8):
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tsi = TSTriple()
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@@ -292,7 +292,7 @@ class Mirny(Module):
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self.sr.ext.cs.eq(eem[3].i),
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]
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- regs = [REG(), REG(width=12), REG(width=4), REG()]
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+ regs = [REG(), REG(width=13), REG(width=4), REG()]
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self.submodules += regs
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for i, reg in enumerate(regs):
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self.sr.connect(reg.bus, adr=i, mask=mask)
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@@ -310,23 +310,47 @@ class Mirny(Module):
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clk = platform.request("clk")
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clk_div = TSTriple()
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self.specials += clk_div.get_tristate(clk.div)
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- # in_sel: 00: XO, 01: MMCX, 10: n/a (SMA+XO), 11: SMA
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+ # in_sel: 00: XO, 01: n/a (SMA+XO), 10: MMCX, 11: SMA
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# dividers: 00(z): 1, 01(z): 1, 10(low): 2, 11(high) 4
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self.comb += [
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Cat(clk.in_sel, clk_div.o, clk_div.oe).eq(regs[1].write[4:8]),
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platform.request("fsen").eq(~regs[1].write[9]),
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]
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- for i, m in enumerate(platform.request("mezz_io")):
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- tsi = TSTriple()
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- self.specials += tsi.get_tristate(m)
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+ if legacy_almazny:
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+ almazny_io = platform.request("legacy_almazny_common")
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+ almazny_adr = 0b1100 # 1100 - and then 1101, 1110, 1111 for sr 1-4
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+ ext = Record(ext_layout)
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+ self.sr.connect_ext(ext, almazny_adr, almazny_adr)
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+ latches = AsyncRst(width=4, reset=0xF)
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+ self.submodules += latches
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+
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self.comb += [
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- tsi.o.eq(regs[3].write[i] | (0 if i >= 4 else
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- (regs[1].write[11] & eem[i + 4].i))),
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- regs[3].read[i].eq(tsi.i),
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- tsi.oe.eq(regs[3].write[i + 8]),
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- regs[3].read[i + 8].eq(tsi.oe),
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+ latches.ce.eq(ext.cs),
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+ almazny_io.clk.eq(ext.sck),
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+ almazny_io.mosi.eq(ext.sdi),
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+ almazny_io.srclr.eq(1)
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]
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+
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+ for i in range(4):
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+ almazny = platform.request("legacy_almazny", i)
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+ self.sync += latches.i[i].eq(self.sr.bus.adr[:2] != i)
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+ self.comb += [
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+ almazny.latch.eq(latches.o[i]),
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+ almazny.noe.eq(~regs[1].write[12])
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+ ]
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+
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+ else:
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+ for i, m in enumerate(platform.request("mezz_io")):
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+ tsi = TSTriple()
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+ self.specials += tsi.get_tristate(m)
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+ self.comb += [
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+ tsi.o.eq(regs[3].write[i] | (0 if i >= 4 else
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+ (regs[1].write[11] & eem[i + 4].i))),
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+ regs[3].read[i].eq(tsi.i),
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+ tsi.oe.eq(regs[3].write[i + 8]),
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+ regs[3].read[i + 8].eq(tsi.oe),
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+ ]
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for i in range(4):
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rf_sw = platform.request("rf_sw", i)
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diff --git a/mirny_cpld.py b/mirny_cpld.py
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index 70fc164..a688d89 100644
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--- a/mirny_cpld.py
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+++ b/mirny_cpld.py
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@@ -16,9 +16,33 @@ _io = [
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# fail save LVDS enable, LVDS mode selection
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# high: type 2 receiver, failsafe low
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("fsen", 0, Pins("P80")),
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-
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+
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+ # IO from 0 to 7
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("mezz_io", 0, Pins("P57 P58 P59 P60 P61 P64 P68 P69")),
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+ # legacy (v1.0-1.1) Almazny pins
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+ ("legacy_almazny_common", 0,
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+ Subsignal("mosi", Pins("P94")),
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+ Subsignal("clk", Pins("P97")),
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+ Subsignal("srclr", Pins("P60")),
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+ ),
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+ ("legacy_almazny", 0,
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+ Subsignal("latch", Pins("P96")),
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+ Subsignal("noe", Pins("P95")),
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+ ),
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+ ("legacy_almazny", 1,
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+ Subsignal("latch", Pins("P100")),
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+ Subsignal("noe", Pins("P98")),
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+ ),
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+ ("legacy_almazny", 2,
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+ Subsignal("latch", Pins("P92")),
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+ Subsignal("noe", Pins("P101")),
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+ ),
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+ ("legacy_almazny", 3,
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+ Subsignal("latch", Pins("P57")),
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+ Subsignal("noe", Pins("P58")),
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+ ),
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+
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("clk", 0,
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Subsignal("div", Pins("P53")),
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Subsignal("in_sel", Pins("P54 P56")),
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diff --git a/mirny_impl.py b/mirny_impl.py
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index 0c42b0b..d7022dc 100644
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--- a/mirny_impl.py
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+++ b/mirny_impl.py
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@@ -1,10 +1,23 @@
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+import argparse
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+
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+def get_argparser():
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+ parser = argparse.ArgumentParser(
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+ description="Mirny CPLD firmware"
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+ )
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+ parser.add_argument("--legacy-almazny", action="store_true", default=False)
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+
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+ return parser
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+
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def main():
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from mirny_cpld import Platform
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from mirny import Mirny
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+ args = get_argparser().parse_args()
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+
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p = Platform()
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- mirny = Mirny(p)
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- p.build(mirny, build_name="mirny", mode="cpld")
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+ mirny = Mirny(p, args.legacy_almazny)
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+ build_name = "mirny" if not args.legacy_almazny else "mirny_legacy_almazny"
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+ p.build(mirny, build_name=build_name, mode="cpld")
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if __name__ == "__main__":
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