humpback-dds/nmigen/fpga_config.py

44 lines
1.1 KiB
Python

# If the design does not create a "sync" clock domain, it is created by the nMigen build system
# using the platform default clock (and default reset, if any).
from nmigen import *
from humpback import *
#class SimpleBlinky(Elaboratable):
# def elaborate(self, platform):
# led = platform.request("user_led", 0)
# counter = Signal(24)
# m = Module()
# m.d.sync += counter.eq(counter + 1)
# m.d.comb += led.o.eq(counter[23])
# return m
# Simple connector from STM32 SPI to Humpback SPI
class UrukulConnector(Elaboratable):
def elaborate(self, platform):
# Acquire SPI slave, EEM port 1 output
spi = platform.request("spi")
print(spi)
eem = platform.request("eem", 1)
print(eem)
clk25 = platform.request("clk25")
counter = Signal(25)
m = Module()
m.domains.sync = ClockDomain()
m.d.comb += ClockSignal().eq(clk25.i)
m.d.sync += counter.eq(counter + 1)
return m
if __name__ == "__main__":
platform = HumpbackPlatform()
platform.add_resources(platform.eem_to_urukul)
platform.add_resources(platform.spi)
platform.build(UrukulConnector(), do_program=False)