cpld: add release

src/cpld.rs

@@ -48,15 +48,20 @@ impl<SPI, CS0, CS1, CS2> CPLD<SPI, CS0, CS1, CS2> where
 		match channel & (1 << 0) {
 			0 => self.chip_select.0.set_low(),
 			_ => self.chip_select.0.set_high(),
-		};
+		}.ok();
 		match channel & (1 << 1) {
 			0 => self.chip_select.1.set_low(),
 			_ => self.chip_select.1.set_high(),
-		};
+		}.ok();
 		match channel & (1 << 2) {
 			0 => self.chip_select.2.set_low(),
 			_ => self.chip_select.2.set_high(),
-		};
+		}.ok();
+	}
+
+	// Return the SPI and CS pins
+	pub fn release(self) -> (SPI, (CS0, CS1, CS2)) {
+		return (self.spi, self.chip_select);
 	}
 
 }