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fpga: allow selecting the Humpback EEM port

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This commit is contained in:
Etienne Wodey 2024-04-24 14:16:19 +02:00
parent 4dabb16b4e
commit 6212ed09ea
2 changed files with 37 additions and 25 deletions
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2
README.md
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@ -14,7 +14,7 @@ Once you have Flakes enabled, you can use ``nix build`` to build the firmware.
Alternatively, you can develop and build it within Nix shell: Alternatively, you can develop and build it within Nix shell:
```shell ```shell
nix develop nix develop
python fpga/fpga_config.py python fpga/fpga_config.py [--eem [0,1,2]]
cargo build --release cargo build --release
``` ```

58
fpga/fpga_config.py
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@ -1,3 +1,5 @@
import argparse
# Import built in I/O, Connectors & Platform template for Humpback # Import built in I/O, Connectors & Platform template for Humpback
from migen.build.platforms.sinara import humpback from migen.build.platforms.sinara import humpback
# Import migen pin record structure # Import migen pin record structure
@ -8,7 +10,7 @@ from migen.genlib.io import *
class UrukulConnector(Module): class UrukulConnector(Module):
def __init__(self, platform): def __init__(self, platform, eem_resource_name):
# Include extension # Include extension
spi_mosi = [ spi_mosi = [
("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33")) ("spi_mosi", 0, Pins("B16"), IOStandard("LVCMOS33"))
@ -26,16 +28,16 @@ class UrukulConnector(Module):
platform.add_extension(spi_mosi) platform.add_extension(spi_mosi)
# Request EEM I/O & SPI # Request EEM I/O & SPI
eem0 = [ eem = [
platform.request("eem0", 0), platform.request(eem_resource_name, 0),
platform.request("eem0", 1), platform.request(eem_resource_name, 1),
# Supply EEM pin with negative polarity # Supply EEM pin with negative polarity
# See issue/PR: https://github.com/m-labs/migen/pull/181 # See issue/PR: https://github.com/m-labs/migen/pull/181
platform.request("eem0_n", 2), platform.request(f"{eem_resource_name}_n", 2),
platform.request("eem0", 3), platform.request(eem_resource_name, 3),
platform.request("eem0", 4), platform.request(eem_resource_name, 4),
platform.request("eem0", 5), platform.request(eem_resource_name, 5),
platform.request("eem0", 6) platform.request(eem_resource_name, 6)
] ]
spi = platform.request("spi") spi = platform.request("spi")
spi_mosi = platform.request("spi_mosi") spi_mosi = platform.request("spi_mosi")
@ -56,37 +58,47 @@ class UrukulConnector(Module):
self.specials += Instance("SB_IO", self.specials += Instance("SB_IO",
p_PIN_TYPE=C(0b000001, 6), p_PIN_TYPE=C(0b000001, 6),
p_IO_STANDARD="SB_LVDS_INPUT", p_IO_STANDARD="SB_LVDS_INPUT",
io_PACKAGE_PIN=eem0[2], io_PACKAGE_PIN=eem[2],
o_D_IN_0=self.miso_n o_D_IN_0=self.miso_n
) )
# Link EEM to SPI # Link EEM to SPI
self.comb += [ self.comb += [
eem0[0].p.eq(spi.clk), eem[0].p.eq(spi.clk),
eem0[0].n.eq(~spi.clk), eem[0].n.eq(~spi.clk),
eem0[1].p.eq(spi_mosi), eem[1].p.eq(spi_mosi),
eem0[1].n.eq(~spi_mosi), eem[1].n.eq(~spi_mosi),
spi.miso.eq(~self.miso_n), spi.miso.eq(~self.miso_n),
eem0[3].p.eq(spi_cs[0]), eem[3].p.eq(spi_cs[0]),
eem0[3].n.eq(~spi_cs[0]), eem[3].n.eq(~spi_cs[0]),
eem0[4].p.eq(spi_cs[1]), eem[4].p.eq(spi_cs[1]),
eem0[4].n.eq(~spi_cs[1]), eem[4].n.eq(~spi_cs[1]),
eem0[5].p.eq(spi_cs[2]), eem[5].p.eq(spi_cs[2]),
eem0[5].n.eq(~spi_cs[2]), eem[5].n.eq(~spi_cs[2]),
eem0[6].p.eq(io_update), eem[6].p.eq(io_update),
eem0[6].n.eq(~io_update), eem[6].n.eq(~io_update),
led.eq(1) led.eq(1)
] ]
if __name__ == "__main__": if __name__ == "__main__":
parser = argparse.ArgumentParser(description="Build FPGA bitstream")
parser.add_argument(
"--eem",
type=int,
choices=[0, 1, 2],
default=0,
help="The Humpback EEM port the Urukul board is connected to."
)
args = parser.parse_args()
platform = humpback.Platform() platform = humpback.Platform()
platform.build(UrukulConnector(platform)) platform.build(UrukulConnector(platform, f"eem{args.eem}"))