From 3abc0c3e4e496fa0b7e0a20071cd1b488abc65a6 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Tue, 29 Sep 2020 14:21:26 +0800
Subject: [PATCH] dds: improve comment

---
 src/dds.rs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/dds.rs b/src/dds.rs
index 3e85ce5..5a0958c 100644
--- a/src/dds.rs
+++ b/src/dds.rs
@@ -187,6 +187,9 @@ where
     }
 
     // Change external clock source (ref_clk)
+    // This will always provide a legitimate f_sys_clk by the following priority
+    // 1. Keep DDS clock tree untouched, record the new f_sys_clk
+    // 2. Use the default divided-by-2 clock tree, if PLL configuration becomes invalid
     pub fn set_ref_clk_frequency(&mut self, f_ref_clk: f64) -> Result<(), Error<E>> {
         // Override old reference clock frequency (ref_clk)
         self.f_ref_clk = f_ref_clk;