From 2ef6bb393c51bc747445f3b1466e0b3b0afc650a Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Wed, 23 Sep 2020 12:33:22 +0800
Subject: [PATCH] urukul: add master clock div getter

---
 src/config_register.rs |  1 -
 src/lib.rs             | 11 ++++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/config_register.rs b/src/config_register.rs
index acf3e14..324fb3e 100644
--- a/src/config_register.rs
+++ b/src/config_register.rs
@@ -75,7 +75,6 @@ where
 
 	/*
 	 * Return selected configuration field
-	 * TODO: Return result type instead for error checking
 	 */
 	pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
 		config_type.get_filtered_content(self.data) as u8
diff --git a/src/lib.rs b/src/lib.rs
index 76ee06d..0a65ad3 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -231,7 +231,7 @@ where
 
 	fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
 		// Calculate reference clock frequency after clock division from configuration register
-		let f_ref_clk = self.f_master_clk / (self.config_register.get_configuration(CFGMask::DIV) as f64);
+		let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
 
 		// Update all DDS chips on reference clock frequency
 		for dds_channel in 0..4 {
@@ -240,6 +240,15 @@ where
 		Ok(())
 	}
 
+	fn get_master_clock_division(&mut self) -> u8 {
+		match self.config_register.get_configuration(CFGMask::DIV) {
+			0 | 3 => 4,
+			1 => 1,
+			2 => 2,
+			_ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
+		}
+	}
+
 	fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
 		if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
 			return Err(Error::ParameterError);