forked from sinara-hw/datasheets
286 lines
9.6 KiB
TeX
286 lines
9.6 KiB
TeX
\documentclass[10pt]{datasheet}
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\usepackage{palatino}
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\usepackage{textgreek}
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\usepackage{minted}
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\usepackage{tcolorbox}
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\usepackage{etoolbox}
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\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}%
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\AfterEndEnvironment{minted}{\end{tcolorbox}}%
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\usepackage[justification=centering]{caption}
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\usepackage[utf8]{inputenc}
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\usepackage[english]{babel}
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\usepackage[english]{isodate}
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\usepackage{graphicx}
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\usepackage{subfigure}
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\usepackage{tikz}
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\usepackage{pgfplots}
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\usepackage{circuitikz}
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\usetikzlibrary{calc}
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\usetikzlibrary{fit,backgrounds}
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\title{5432 Zotino}
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\author{M-Labs Limited}
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\date{December 2021}
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\revision{Revision 1}
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\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
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\begin{document}
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\maketitle
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\section{Features}
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\begin{itemize}
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\item{32-channels DAC.}
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\item{16-bits resolution.}
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\item{1 MSPS shared between all channels.}
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\item{Output voltage $\pm$10V.}
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\item{HD68 connector.}
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\item{Can be broken out to BNC/SMA/MCX.}
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\end{itemize}
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\section{Applications}
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\begin{itemize}
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\item{Controlling setpoints of PID controllers for laser power stabilization.}
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\item{Low-frequency arbitrary waveform generation.}
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\item{Driving DC electrodes in ion traps.}
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\end{itemize}
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\section{General Description}
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The 5432 Zotino is a 4hp EEM module part of the ARTIQ Sinara family.
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It adds digital-analog converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
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It provides 4 groups of 8 analog channels each, exposed by 1 HD68 connector.
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Each channel supports output voltage from -10 V to 10 V.
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All channels can be updated simultaneously.
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% Switch to next column
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\vfill\break
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\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
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\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
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\begin{figure}[h]
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\centering
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\scalebox{0.88}{
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\begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
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% HD68 Connector
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\draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
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% EEM Connectors to IDC cards
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\draw (2.2, 1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
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\draw (1.4, 1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
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\draw (2.2, -1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
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\draw (1.4, -1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
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% Op-amp x32
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\draw (3.6, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
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% DAC AD5372
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\draw (5.2, 0) node[twoportshape, t={DAC}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (dac) {};
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% LVDS Transceivers
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\draw (6.6, 1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
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\draw (6.6, -1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
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% Aesthetic EEPROM
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\draw (6.6, 0) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) {};
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% EEMs from core device / controllers
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\draw (8.2, 0.0) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem_in) {};
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% Connect EEM IN to LVDS & EEMPROM
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\draw [latexslim-latexslim] (eeprom.north) -- (7.85, 0);
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\draw [latexslim-latexslim] (lvds0.north) -- (7.85, 1.6);
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\draw [latexslim-latexslim] (lvds1.north) -- (7.85, -1.6);
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% Connect LVDS to DAC
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\draw [latexslim-latexslim] (lvds0.south) -- (5.2, 1.6) -- (dac.north);
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\draw [latexslim-latexslim] (lvds1.south) -- (5.2, -1.6) -- (dac.south);
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% Connect DAC to Op-amp, label op-amp width x32
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\draw [-latexslim] (dac.west) -- (amp.west);
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\node [label=below:\tiny{Op-amp x32}] at (3.6, -0.2) {};
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\node [label=below:\tiny{1 per ch.}] at (3.6, -0.45) {};
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% Connect Op-amp to EEM OUT and HD68
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\draw [-latexslim] (amp.east) -- (hd68.east);
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\draw [-latexslim] (2.2, 0) -- (eem2.east);
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\draw [-latexslim] (1.4, 0) -- (eem3.east);
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\draw [-latexslim] (2.2, 0) -- (eem1.west);
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\draw [-latexslim] (1.4, 0) -- (eem0.west);
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\end{circuitikz}
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}
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\caption{Simplified Block Diagram}
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\end{figure}
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\begin{figure}[h]
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\centering
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\includegraphics[height=2in]{Zotino_FP.png}
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\includegraphics[height=2in]{photo5432.jpg}
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\caption{Zotino Card photo}
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\end{figure}
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% For wide tables, a single column layout is better. It can be switched
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% page-by-page.
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\onecolumn
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\section{Electrical Specifications}
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Output Specifications}
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\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions} \\
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\hline
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Output voltage & $V_{out}$ & -10 & & 10 & V & \\
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\hline
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Output impedance & $Z_{out}$ & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
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\hline
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Resolution & & & 16 & & bits & \\
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\hline
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3dB bandwidth & & & 75 & & kHz & \\
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\hline
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Power consumption & & 3 & & 8.7 & W & \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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Output noise are measured after 15 cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF. The DAC output is 3.5 V.
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\begin{table}[h]
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\begin{threeparttable}
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\caption{Electrical Characteristics}
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\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
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\thickhline
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\textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
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\textbf{Unit} & \textbf{Conditions / Comments} \\
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\hline
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DC cross-talk & & & -116 & & dB & \\
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\hline
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Fall-time & & & 18.5 & & $\mu$s & 10\% to 90\% fall-time \\
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& & & 25 & & $\mu$s & 1\% to 99\% fall-time \\
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\hline
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Negative overshoot & & & 0.5\% & & - & \\
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\hline
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Rise-time & & & 30 & & $\mu$s & 1\% to 99\% rise-time \\
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\hline
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Positive overshoot & & & 0.65\% & & - & \\
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\hline
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Output noise & & & & & & \\
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\hspace{18mm} @ 100 Hz & & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
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\hspace{18mm} @ 300 Hz & & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
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\hspace{18mm} @ 50 kHz & & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
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\hspace{18mm} @ 1 MHz & & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
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\hspace{18mm} $>$ 4 MHz & & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
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\thickhline
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\end{tabularx}
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\end{threeparttable}
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\end{table}
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\newpage
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\begin{figure}[h]
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\centering
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\includegraphics[width=3.3in]{zotino_step_response_rising.png}
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\caption{Step response (switching from -10V to +10V)}
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\end{figure}
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\begin{figure}[h]
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\centering
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\includegraphics[width=3.3in]{zotino_step_response_falling.png}
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\caption{Step response (switching from +10V to -10V)}
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\end{figure}
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\begin{figure}[hbt!]
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\centering
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\includegraphics[width=3.3in]{zotino_fext.png}
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\caption{Step crosstalk}
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\end{figure}
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\newpage
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\section{Example ARTIQ code}
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The sections below demonstrate simple usage scenarios of the 5432 Zotino card with the ARTIQ control system.
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They do not exhaustively demonstrate all the features of the ARTIQ system.
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The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
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\subsection{Set output voltage}
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The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channel 0, 1, 2, 3 respectively.
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Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
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\begin{minted}{python}
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def prepare(self):
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self.channels = [0, 1, 2, 3]
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self.voltages = [1.0, 2.0, 3.0, 4.0]
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.zotino.init()
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delay(1*ms)
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self.zotino.set_dac(self.voltages, self.channels)
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\end{minted}
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\subsection{Triangular Wave}
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A triangular waveform at 10 Hz, 16 V peak-to-peak.
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Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
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\begin{minted}{python}
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from scipy import signal
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import numpy
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def prepare(self):
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self.period = 0.1*s
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self.sample = 128
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t = numpy.linspace(0, 1, self.sample)
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self.voltages = 8*signal.sawtooth(2*numpy.pi*t, 0.5)
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self.interval = self.period/self.sample
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.zotino.init()
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delay(1*ms)
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counter = 0
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while True:
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self.zotino.set_dac([self.voltages[counter]], [0])
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counter = (counter + 1) % self.sample
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delay(self.interval)
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\end{minted}
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\section{Front Panel Drawings}
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\begin{figure}[hbt!]
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\centering
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\includegraphics[height=2in]{Zotino_drawings.jpg}
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\includegraphics[height=2in]{Zotino_assembly.jpg}
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\caption{5432 Zotino front panel drawings.}
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\end{figure}
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\section{Ordering Information}
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To order, please visit \url{https://m-labs.hk} and select the 5432 Zotino in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
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\section*{}
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\vspace*{\fill}
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\begin{footnotesize}
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Information furnished by M-Labs Limited is believed to be accurate and reliable. However, no responsibility is assumed by M-Labs Limited for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
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Specifications subject to change without notice.
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\end{footnotesize}
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\end{document}
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