5432: init

5432.tex

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+\documentclass[10pt]{datasheet}
+\usepackage{palatino}
+\usepackage{textgreek}
+\usepackage{minted}
+\usepackage{tcolorbox}
+\usepackage{etoolbox}
+\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}%
+\AfterEndEnvironment{minted}{\end{tcolorbox}}%
+
+\usepackage[justification=centering]{caption}
+
+\usepackage[utf8]{inputenc}
+\usepackage[english]{babel}
+\usepackage[english]{isodate}
+
+\usepackage{graphicx}
+\usepackage{subfigure}
+
+\usepackage{tikz}
+\usepackage{pgfplots}
+\usepackage{circuitikz}
+\usetikzlibrary{calc}
+\usetikzlibrary{fit,backgrounds} 
+
+\title{5432 Zotino}
+\author{M-Labs Limited}
+\date{December 2021}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{32-channels DAC.}
+\item{16-bits resolution.}
+\item{1 MSPS shared between all channels.}
+\item{Output voltage $\pm$10V.}
+\item{HD68 connector.}
+\item{Can be broken out to BNC/SMA/MCX.}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Variable optical attenuators (VOA).}
+\item{Optical switches.}
+\item{Industrial control systems.}
+\end{itemize}
+
+\section{General Description}
+The 5432 Zotino is a 4hp EEM module part of the ARTIQ Sinara family.
+It adds digital-analog converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+It provides 4 groups of 8 analog channels each, exposed by 1 HD68 connector.
+Each channel supports output voltage from -10 V to 10 V.
+All channels can be updated simultaneously.
+
+% Switch to next column
+\vfill\break
+
+\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
+\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % HD68 Connector
+        \draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
+
+        % EEM Connectors to IDC cards
+        \draw (2.2, 1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
+        \draw (1.4, 1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
+        \draw (2.2, -1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
+        \draw (1.4, -1.2) node[twoportshape, t={\MyLabel{EEM}{ADC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
+
+        % Op-amp x32
+        \draw (3.6, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
+
+        % DAC AD5372
+        \draw (5.2, 0) node[twoportshape, t={DAC}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (dac) {};
+
+        % LVDS Transceivers
+        \draw (6.6, 1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
+        \draw (6.6, -1.6) node[twoportshape, t=\MymyLabel{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
+
+        % Aesthetic EEPROM
+        \draw (6.6, 0) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) {};
+
+        % EEMs from core device / controllers
+        \draw (8.2, 0.0) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem_in) {};
+
+        % Connect EEM IN to LVDS & EEMPROM
+        \draw [latexslim-latexslim] (eeprom.north) -- (7.85, 0);
+        \draw [latexslim-latexslim] (lvds0.north) -- (7.85, 1.6);
+        \draw [latexslim-latexslim] (lvds1.north) -- (7.85, -1.6);
+
+        % Connect LVDS to DAC
+        \draw [latexslim-latexslim] (lvds0.south) -- (5.2, 1.6) -- (dac.north);
+        \draw [latexslim-latexslim] (lvds1.south) -- (5.2, -1.6) -- (dac.south);
+
+        % Connect DAC to Op-amp, label op-amp width x32
+        \draw [-latexslim] (dac.west) -- (amp.west);
+        \node [label=below:\tiny{Op-amp x32}] at (3.6, -0.2) {};
+
+        % Connect Op-amp to EEM OUT and HD68
+        \draw [-latexslim] (amp.east) -- (hd68.east);
+        \draw [-latexslim] (2.2, 0) -- (eem2.east);
+        \draw [-latexslim] (1.4, 0) -- (eem3.east);
+        \draw [-latexslim] (2.2, 0) -- (eem1.west);
+        \draw [-latexslim] (1.4, 0) -- (eem0.west);
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[h]
+    \centering
+    \includegraphics[width=3in]{photo5432.jpg}
+    \caption{Zotino Card photo}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\section{Electrical Specifications}
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Output Specifications}
+\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Output voltage & $V_{out}$ & -10 & & 10 & V & \\
+    \hline
+    Output impedance & $Z_{out}$ & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
+    \hline
+    Resolution & & & 16 & & bits & \\
+    \hline
+    3dB bandwidth & & & 75 & & kHz & \\
+    \hline
+    Power consumption & & 3 & & 8.7 & W & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+Output noise are measured after 15 cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF. The DAC output is 3.5 V.
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Electrical Characteristics}
+\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions / Comments} \\
+    \hline
+    DC cross-talk & & & -116 & & dB & \\
+    \hline
+    Fall-time & & & 18.5 & & $\mu$s & 10\% to 90\% fall-time \\
+    & & & 25 & & $\mu$s & 1\% to 99\% fall-time \\
+    \hline
+    Negative overshoot & & & 0.5\% & & - & \\
+    \hline
+    Rise-time & & & 30 & & $\mu$s & 1\% to 99\% rise-time \\
+    \hline
+    Positive overshoot & & & 0.65\% & & - & \\
+    \hline
+    Output noise & & & & & & \\
+    \hspace{18mm} @ 100 Hz & & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
+    \hspace{18mm} @ 300 Hz & & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
+    \hspace{18mm} @ 50 kHz & & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
+    \hspace{18mm} @ 1 MHz & & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
+    \hspace{18mm} $>$ 4 MHz & & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\section{Example ARTIQ code}
+The sections below demonstrate simple usage scenarios of the 5432 Zotino card with the ARTIQ control system.
+They do not exhaustively demonstrate all the features of the ARTIQ system.
+The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
+
+\subsection{Set output voltage}
+The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channel 0, 1, 2, 3 respectively.
+Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
+
+\begin{minted}{python}
+def prepare(self):
+    self.channels = [0, 1, 2, 3]
+    self.voltages = [1.0, 2.0, 3.0, 4.0]
+
+@kernel
+def run(self):
+    self.core.reset()
+    self.core.break_realtime()
+    self.zotino.init()
+
+    delay(1*ms)
+    self.zotino.set_dac(self.voltages, self.channels)
+\end{minted}
+
+\subsection{Triangular Wave}
+A triangular waveform at 10 Hz, 16 V peak-to-peak.
+Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
+\begin{minted}{python}
+from scipy import signal
+import numpy
+
+def prepare(self):
+    self.period = 0.1*s
+    self.sample = 128
+    t = numpy.linspace(0, 1, self.sample)
+    self.voltages = 8*signal.sawtooth(2*numpy.pi*t, 0.5)
+    self.interval = self.period/self.sample
+
+@kernel
+def run(self):
+    self.core.reset()
+    self.core.break_realtime()
+    self.zotino.init()
+
+    delay(1*ms)
+
+    counter = 0
+    while True:
+        self.zotino.set_dac([self.voltages[counter]], [0])
+        counter = (counter + 1) % self.sample
+        delay(self.interval)
+\end{minted}
+
+\section{Ordering Information}
+To order, please visit \url{https://m-labs.hk} and select the 2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
+
+\section*{}
+\vspace*{\fill}
+
+\begin{footnotesize}
+Information furnished by M-Labs Limited is believed to be accurate and reliable. However, no responsibility is assumed by M-Labs Limited for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
+Specifications subject to change without notice.
+\end{footnotesize}
+
+\end{document}