forked from sinara-hw/assembly
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9929476733
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a9645c3b03 |
@ -2,6 +2,7 @@
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- [Build and test firmware](./build_test_firmware.md)
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- [Hardware](./hw/hardware.md)
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- [Sinara Kasli](./hw/kasli.md)
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- [Sinara Kasli-SOC](./hw/kasli_soc.md)
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- [Sinara 4624 AWG Phaser (Upconverter/Baseband)](./hw/phaser.md)
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- [Sinara 4456 synthesizer Mirny / Sinara 4457 Almazny Mezzanine card](./hw/mirny_almazny.md)
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@ -17,6 +18,7 @@
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- [Sinara 8452 DSP Stabilizer](./hw/stabilizer.md)
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- [Sinara 9805 RF Power Amplifier Booster](./hw/booster.md)
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- [Sinara 8451 Thermostat](./hw/thermostat.md)
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- [Sinara 2245 LVDS DIO](./hw/lvds_dio.md)
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- [Software/Support](./sw_sup/software_support.md)
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- [Building legacy firmware](./sw_sup/artiq_legacy.md)
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- [Networking](./sw_sup/networking.md)
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BIN
src/extra/booster/booster0.5.0.tar.xz
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BIN
src/extra/booster/booster0.5.0.tar.xz
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Binary file not shown.
BIN
src/extra/booster/kasli-booster.zip
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src/extra/booster/kasli-booster.zip
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Binary file not shown.
@ -8,9 +8,40 @@
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### Flashing
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#### Easier way
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Download and unpack the [booster firmware](../extra/booster/booster0.5.0.tar.xz), and then:
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```shell
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nix-shell -p dfu-util
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dfu-util -a 0 -s 0x08000000:leave --download booster0.5.0.bin
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```
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#### Build from source on Fedora 38
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Creating proper Nix shell for updated Rust is quite troublesome, so the faster way is actually to use any
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classic Linux distribution:
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```shell
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git clone https://github.com/quartiq/booster.git # download sources
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sudo dnf install clang dfu-util
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cd booster/
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curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh # install Rust, we need rustup
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rustup target add thumbv7em-none-eabihf
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cargo install cargo-binutils
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rustup component add llvm-tools-preview
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cargo build --release
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cargo objcopy --release -- -O binary booster.bin
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# enter dfu mode by either serial terminal or
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# press `DFU Bootloader` button while rebooting
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dfu-util -a 0 -s 0x08000000:leave --download booster.bin
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```
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#### For version before September 2023 on NixOS
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```shell
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git clone git@github.com:quartiq/booster.git
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cd booster
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git checkout a1f83b63180511ecd68f88a04621624941d17a41 # or earlier
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nix-shell -p rustup cargo rustc dfu-util
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rustup target add thumbv7em-none-eabihf
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cargo install cargo-binutils
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@ -32,7 +63,7 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
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```
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3. `mosquitto -c mosquitto.conf -d`
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4. Run `cutecom`
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5. Connect to the Booster via `/dev/ttyACMX` port, baud 9600
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5. Connect to the Booster via `/dev/ttyACMX` port, baud 9600, switch from LF to CR on newer version
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6. Send `help` command to check if it works
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7. Enter commands (change details if necessary):
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```shell
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@ -44,6 +75,13 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
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# apply changes and wait until it fully rebooted
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reset
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```
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Newer version:
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```shell
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write broker "192.168.1.123"
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write ip "192.168.1.75"
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# apply changes and wait until it fully rebooted
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reset
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```
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8. Check the Booster connects to your broker.
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9. Download AppImage from [MQTT Explorer](https://mqtt-explorer.com/)
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10. Run it with `appimage-run /path/to/MQTT-Explorer-XXX.AppImage`
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@ -52,15 +90,20 @@ dfu-util -a 0 -s 0x08000000:leave --download booster.bin
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## Calibration
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1. Assemble Kasli with one Urukul, build and flash firmware for it with [booster.json](../extra/booster.json)
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2. Run [dds_for_booster.py](../extra/dds_for_booster.py) experiment once
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1. Assemble Kasli with one Urukul, build and flash firmware for it with [booster.json](../extra/booster/booster.json)
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2. Run [dds_for_booster.py](../extra/booster/dds_for_booster.py) experiment once
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3. Attach parallel 50 Ohm load to the oscilloscope, as shown on the picture: ![](../img/50ohm_parallel_load.jpg),
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4. Configure oscilloscope for 1M Ohm impedance
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5. Attach attenuator to the Urukul's RF2
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6. `cd py/`
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7. You may also need to download or install python's `gmqtt` and `miniconf`
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7. You may also need to download or install python's `gmqtt` and `miniconf`:
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```shell
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python -m venv env
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source env/bin/activate.fish
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pip install git+https://github.com/quartiq/miniconf.git@84cc9046bf504cc2d0d33b84d2f3133f2faf2248#subdirectory=py/miniconf-mqtt
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```
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8. Enable channels: `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N tune=0.1`
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9. Using [booster_template](../extra/booster_template.ods) fill in `y0`, `y1`, `m`, `c`, values using instructions below
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9. Using [booster_template](../extra/booster/booster_template.ods) fill in `y0`, `y1`, `m`, `c`, values using instructions below
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10. Update settings with the adjusted values
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11. Save settings with `python -m booster --broker 192.168.1.123 --prefix dt/sinara/booster/xx-xx-xx-xx-xx-xx --channel N save`
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12. Reboot and check settings are applied
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9
src/hw/kasli.md
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9
src/hw/kasli.md
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@ -0,0 +1,9 @@
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# Kasli
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## Mounting fan onto heatsink
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![](../img/kasli_fan.jpg)
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1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
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2. Place the fan on a heatsink
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3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
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4. Replace the tapping screws with M2.5x14mm screws
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5. Verify the fan is secure
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@ -5,4 +5,12 @@
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Check the BOOT mode switches - they both should be at SD if the Kasli-SoC going to be shipped to customer.
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POR jumper needs only for JTAG mode.
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![](../img/kasli_soc.jpg)
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![](../img/kasli_soc.jpg)
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## Mounting fan onto heatsink
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![](../img/kasli_soc_fan.jpg)
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1. ⚠️ Verify the fan has the **correct polarity (powering on with wrong polarity will burn the MOSFET in series💥)**
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2. Place the fan on a heatsink
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3. Tap 3 threads on the heatsink using M2.5 pointy tapping screws (e.g. front panel screws)
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4. Replace the tapping screws with M2.5x14mm screws
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5. Verify the fan is secure
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38
src/hw/lvds_dio.md
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38
src/hw/lvds_dio.md
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@ -0,0 +1,38 @@
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# Sinara 2245 LVDS DIO card
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* [Wiki](https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki)
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* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/2245.pdf)
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## JSON
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Be aware of the reversed EEM order on the card:
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```json
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[
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{
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"type": "dio",
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"board": "DIO_LVDS",
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"ports": [1],
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"bank_direction_low": "input",
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"bank_direction_high": "input",
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"edge_counter": false // or true
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},
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{
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"type": "dio",
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"board": "DIO_LVDS",
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"ports": [0],
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"bank_direction_low": "output",
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"bank_direction_high": "output"
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}
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]
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```
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## Setup
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Switch DIPs in required position per each channel individually. Each RJ45 have 4 channels.
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## Testing
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You can test channels by connecting Ethernet RJ45 cable. Since the artiq_sinara_tester allows to choose only one DIO
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port, you will need to run the test 4 times and choose different output source and track that every 4th is passing the test.
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It is also incompatible with other TTL cards, so you will need to use same or other LVDS card for proper testing.
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@ -30,6 +30,22 @@ Synchronization requires Kasli and Urukul to be clocked from the same oscillator
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why this feature is disabled by default.
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There is no intrinsic impact on Urukul output phase noise and the synchronization process is quick and reliable when done correctly.
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### One-EEM mode
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Users may choose to use only one EEM port, if they want more cards to be in their crate. However following features
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will become unavailable:
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* SU-Servo
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* Low-latency RF switch control
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* Synchronization
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RF switches are still available but the commands need to go over the SPI bus so it's higher-latency and lower-resolution.
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### Urukul 4412
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Urukul 4412 has higher frequency resolution (47 bit against 32 at Urukul 4410), however lacks such features:
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* SU-Servo
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* Synchronization
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## Testing
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After running `artiq_sinara_test`:
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@ -132,4 +148,25 @@ matches real clocker source.
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ValueError: Urukul AD9910 AUX_DAC mismatch
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```
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Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
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Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description.
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### Jagged signal with 1GHz external clock on AD9910
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By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled.
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Change the ``clk_div`` parameter to the CPLD in the device_db file:
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```python
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device_db["urukulX_cpld"] = {
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"sync_device": None,
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 1000000000.0,
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"clk_sel": 1,
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"clk_div" : 1 # <--- add this line
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}
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}
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```
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@ -55,4 +55,20 @@ Press ENTER when done.
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### High-freq audible noise and output values all near -0.1 on Zotino v1.4.2
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This may happen when power-cycle is too short. Power down the crate, wait at least 30 seconds, and power up again.
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[Issue](https://github.com/sinara-hw/Zotino/issues/37).
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[Issue](https://github.com/sinara-hw/Zotino/issues/37).
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### Zero voltage output on Fastino
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Some Fastino may not output any voltage during testing, usually that means it has no gateware.
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Another common symptom of no gateware is that no LEDs are lit up. Whereas if the gateware has been flashed, the PG and FD LEDs will be lit green.
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You can flash the gateware with a standalone Kasli/Kasli-SoC:
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1. Download the latest `fastino.bin` release from [quartiq/fastino](https://github.com/quartiq/fastino/releases)
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2. Run `git clone https://github.com/quartiq/kasli-i2c.git` and place `fastino.bin` in the kasli-i2c directory
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2. Connect the Fastino's EEM0 to any available Kasli/Kasli-SoC EEM port (**do not hot-plug**)
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3. Power on the standalone Kasli/Kasli-SoC
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4. Run `nix-shell -p python311Packages.pyftdi`
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5. Run `cd kasli-i2c; python flash_fastino.py 0 EEM<number> write fastino.bin` where `<number>` is the EEM port number on the Kasli/Kasli-SoC side
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6. If PG and FD LEDs are lit green, the Fastino is ready.
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BIN
src/img/kasli_fan.jpg
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src/img/kasli_fan.jpg
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After Width: | Height: | Size: 134 KiB |
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src/img/kasli_soc_fan.jpg
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src/img/kasli_soc_fan.jpg
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After Width: | Height: | Size: 216 KiB |
@ -3,8 +3,7 @@
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This page describes ways to set up clocking. Official documentation references:
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* [Carrier configuration](https://m-labs.hk/artiq/manual/installing.html#miscellaneous-configuration-of-the-core-device)
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*
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Devices' [available options](https://m-labs.hk/artiq/manual/core_drivers_reference.html), [Urukul example](https://m-labs.hk/artiq/manual/core_drivers_reference.html#artiq.coredevice.urukul.CPLD)
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* Devices' [available options](https://m-labs.hk/artiq/manual/core_drivers_reference.html), [Urukul example](https://m-labs.hk/artiq/manual/core_drivers_reference.html#artiq.coredevice.urukul.CPLD)
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In general, any RF card and Carriers require some clock source. Most of them have both internal clock signal generator
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and external MMCX and/or SMA connectors to accept the signal. By default the internal clock is used for Carriers,
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@ -60,7 +59,11 @@ so Urukul entry may look like this:
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```json
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{
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"type": "urukul", "dds": "ad9910", "ports": [1, 2], "refclk": 10e6, "clk_sel": 1
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"type": "urukul",
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"dds": "ad9910",
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"ports": [1, 2],
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"refclk": 10e6,
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"clk_sel": 1
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}
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```
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