From 9929476733f884344bab6f31c06e8f6a3f031926 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 16 Feb 2024 12:30:09 +0800 Subject: [PATCH] urukul: add note on clk_div with pll disabled --- src/hw/urukul.md | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/hw/urukul.md b/src/hw/urukul.md index 4fa5539..c50fd01 100644 --- a/src/hw/urukul.md +++ b/src/hw/urukul.md @@ -148,4 +148,25 @@ matches real clocker source. ValueError: Urukul AD9910 AUX_DAC mismatch ``` -Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description. \ No newline at end of file +Ensure it is the AD9910 and not the AD9912. Also check SUServo pins are set up respective to the JSON description. + +### Jagged signal with 1GHz external clock on AD9910 + +By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled. +Change the ``clk_div`` parameter to the CPLD in the device_db file: + +```python +device_db["urukulX_cpld"] = { + "type": "local", + "module": "artiq.coredevice.urukul", + "class": "CPLD", + "arguments": { + "spi_device": "spi_urukul0", + "sync_device": None, + "io_update_device": "ttl_urukul0_io_update", + "refclk": 1000000000.0, + "clk_sel": 1, + "clk_div" : 1 # <--- add this line + } +} +``` \ No newline at end of file