forked from M-Labs/artiq-zynq
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master
Author | SHA1 | Date | |
---|---|---|---|
5582ca74d2 | |||
7c741d9c18 | |||
922a03b807 | |||
716a5924d1 | |||
4856cddb65 |
20
flake.lock
generated
20
flake.lock
generated
@ -11,11 +11,11 @@
|
|||||||
"src-pythonparser": "src-pythonparser"
|
"src-pythonparser": "src-pythonparser"
|
||||||
},
|
},
|
||||||
"locked": {
|
"locked": {
|
||||||
"lastModified": 1732066716,
|
"lastModified": 1733894986,
|
||||||
"narHash": "sha256-krjvt9+RccnAxSEZcFhRpjA2S3CoqE4MSa1JUg421b4=",
|
"narHash": "sha256-zwMs87eUiVURXqavNYL42ZGi+INA7AXHUkx+go9dCLs=",
|
||||||
"ref": "refs/heads/master",
|
"ref": "refs/heads/master",
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||||||
"rev": "270a417a28b516d36983779a1adb6d33a3c55a4a",
|
"rev": "3db8d2310cb45989a7fb4408508013ea1c03f7b9",
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||||||
"revCount": 9102,
|
"revCount": 9113,
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||||||
"type": "git",
|
"type": "git",
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||||||
"url": "https://github.com/m-labs/artiq.git"
|
"url": "https://github.com/m-labs/artiq.git"
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||||||
},
|
},
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||||||
@ -70,11 +70,11 @@
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|||||||
},
|
},
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||||||
"nixpkgs": {
|
"nixpkgs": {
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||||||
"locked": {
|
"locked": {
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||||||
"lastModified": 1731319897,
|
"lastModified": 1733759999,
|
||||||
"narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
|
"narHash": "sha256-463SNPWmz46iLzJKRzO3Q2b0Aurff3U1n0nYItxq7jU=",
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||||||
"owner": "NixOS",
|
"owner": "NixOS",
|
||||||
"repo": "nixpkgs",
|
"repo": "nixpkgs",
|
||||||
"rev": "dc460ec76cbff0e66e269457d7b728432263166c",
|
"rev": "a73246e2eef4c6ed172979932bc80e1404ba2d56",
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||||||
"type": "github"
|
"type": "github"
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||||||
},
|
},
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||||||
"original": {
|
"original": {
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||||||
@ -142,11 +142,11 @@
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|||||||
]
|
]
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||||||
},
|
},
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||||||
"locked": {
|
"locked": {
|
||||||
"lastModified": 1728371104,
|
"lastModified": 1733319649,
|
||||||
"narHash": "sha256-PPnAyDedUQ7Og/Cby9x5OT9wMkNGTP8GS53V6N/dk4w=",
|
"narHash": "sha256-ATJV2UV9FXEiTF6/1BvZ2HmB0goF5TZ2ytgRBwD/BGg=",
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||||||
"owner": "m-labs",
|
"owner": "m-labs",
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||||||
"repo": "sipyco",
|
"repo": "sipyco",
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||||||
"rev": "094a6cd63ffa980ef63698920170e50dc9ba77fd",
|
"rev": "27312727bdb8a182bd6e222e4cbdd3f39ae41d4e",
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||||||
"type": "github"
|
"type": "github"
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||||||
},
|
},
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||||||
"original": {
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"original": {
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|
@ -11,6 +11,7 @@
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zynqpkgs = zynq-rs.packages.x86_64-linux;
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zynqpkgs = zynq-rs.packages.x86_64-linux;
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artiqpkgs = artiq.packages.x86_64-linux;
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artiqpkgs = artiq.packages.x86_64-linux;
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llvmPackages_11 = zynq-rs.llvmPackages_11;
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llvmPackages_11 = zynq-rs.llvmPackages_11;
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|
zynqRev = self.sourceInfo.rev or "unknown";
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|
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rust = zynq-rs.rust;
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rust = zynq-rs.rust;
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rustPlatform = zynq-rs.rustPlatform;
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rustPlatform = zynq-rs.rustPlatform;
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@ -137,6 +138,7 @@
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llvmPackages_11.clang-unwrapped
|
llvmPackages_11.clang-unwrapped
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||||||
];
|
];
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buildPhase = ''
|
buildPhase = ''
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|
export ZYNQ_REV=${zynqRev}
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export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
|
export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
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export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
|
export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
|
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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@ -164,6 +166,7 @@
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];
|
];
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}
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}
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''
|
''
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|
export ZYNQ_REV=${zynqRev}
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python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
|
python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
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mkdir -p $out $out/nix-support
|
mkdir -p $out $out/nix-support
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cp build/top.bit $out
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cp build/top.bit $out
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@ -386,6 +389,7 @@
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binutils-arm
|
binutils-arm
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pre-commit
|
pre-commit
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];
|
];
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|
ZYNQ_REV="${zynqRev}";
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XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
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XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
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CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
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CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
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ZYNQ_RS = "${zynq-rs}";
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ZYNQ_RS = "${zynq-rs}";
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@ -1,5 +1,15 @@
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|
import os
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from artiq._version import get_version
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from misoc.integration import cpu_interface
|
from misoc.integration import cpu_interface
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|
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|
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|
def generate_ident(variant):
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|
return "{}+{};{}".format(
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|
get_version().split(".")[0],
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os.getenv("ZYNQ_REV", default="unknown")[:8],
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|
variant,
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|
)
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|
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def write_csr_file(soc, filename):
|
def write_csr_file(soc, filename):
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with open(filename, "w") as f:
|
with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
|
f.write(cpu_interface.get_csr_rust(
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|
@ -7,7 +7,7 @@ import dma
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from artiq.gateware import rtio
|
from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import spi2, ttl_simple
|
from artiq.gateware.rtio.phy import spi2, ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
|
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
|
from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
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from migen import *
|
from migen import *
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from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
|
from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
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from migen.build.platforms import ebaz4205
|
from migen.build.platforms import ebaz4205
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@ -125,7 +125,7 @@ class EBAZ4205(SoCCore):
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"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
|
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
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)
|
)
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|
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ident = self.__class__.__name__
|
ident = generate_ident(self.__class__.__name__)
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if self.acpki:
|
if self.acpki:
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ident = "acpki_" + ident
|
ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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|
@ -24,10 +24,10 @@ from artiq.gateware.wrpll import wrpll
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|
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import dma
|
import dma
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import analyzer
|
import analyzer
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import acpki
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import acpki as acpki_lib
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import drtio_aux_controller
|
import drtio_aux_controller
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import zynq_clocking
|
import zynq_clocking
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
|
from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
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|
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eem_iostandard_dict = {
|
eem_iostandard_dict = {
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0: "LVDS_25",
|
0: "LVDS_25",
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@ -115,7 +115,7 @@ class GenericStandalone(SoCCore):
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platform.toolchain.bitstream_commands.extend([
|
platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
||||||
])
|
])
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ident = description["variant"]
|
ident = generate_ident(description["variant"])
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if self.acpki:
|
if self.acpki:
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ident = "acpki_" + ident
|
ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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@ -184,10 +184,10 @@ class GenericStandalone(SoCCore):
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|
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if self.acpki:
|
if self.acpki:
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self.config["KI_IMPL"] = "acp"
|
self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
|
bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
|
user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
|
evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
|
self.csr_devices.append("rtio")
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else:
|
else:
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self.config["KI_IMPL"] = "csr"
|
self.config["KI_IMPL"] = "csr"
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@ -229,7 +229,7 @@ class GenericMaster(SoCCore):
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platform.toolchain.bitstream_commands.extend([
|
platform.toolchain.bitstream_commands.extend([
|
||||||
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
||||||
])
|
])
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||||||
ident = description["variant"]
|
ident = generate_ident(description["variant"])
|
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if self.acpki:
|
if self.acpki:
|
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ident = "acpki_" + ident
|
ident = "acpki_" + ident
|
||||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
||||||
@ -349,10 +349,10 @@ class GenericMaster(SoCCore):
|
|||||||
|
|
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if self.acpki:
|
if self.acpki:
|
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self.config["KI_IMPL"] = "acp"
|
self.config["KI_IMPL"] = "acp"
|
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
|
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bus=self.ps7.s_axi_acp,
|
bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
|
user=self.ps7.s_axi_acp_user,
|
||||||
evento=self.ps7.event.o)
|
evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
|
self.csr_devices.append("rtio")
|
||||||
else:
|
else:
|
||||||
self.config["KI_IMPL"] = "csr"
|
self.config["KI_IMPL"] = "csr"
|
||||||
@ -438,7 +438,7 @@ class GenericSatellite(SoCCore):
|
|||||||
platform.toolchain.bitstream_commands.extend([
|
platform.toolchain.bitstream_commands.extend([
|
||||||
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
||||||
])
|
])
|
||||||
ident = description["variant"]
|
ident = generate_ident(description["variant"])
|
||||||
if self.acpki:
|
if self.acpki:
|
||||||
ident = "acpki_" + ident
|
ident = "acpki_" + ident
|
||||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
||||||
@ -544,10 +544,10 @@ class GenericSatellite(SoCCore):
|
|||||||
|
|
||||||
if self.acpki:
|
if self.acpki:
|
||||||
self.config["KI_IMPL"] = "acp"
|
self.config["KI_IMPL"] = "acp"
|
||||||
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
|
||||||
bus=self.ps7.s_axi_acp,
|
bus=self.ps7.s_axi_acp,
|
||||||
user=self.ps7.s_axi_acp_user,
|
user=self.ps7.s_axi_acp_user,
|
||||||
evento=self.ps7.event.o)
|
evento=self.ps7.event.o)
|
||||||
self.csr_devices.append("rtio")
|
self.csr_devices.append("rtio")
|
||||||
else:
|
else:
|
||||||
self.config["KI_IMPL"] = "csr"
|
self.config["KI_IMPL"] = "csr"
|
||||||
|
@ -25,7 +25,7 @@ import analyzer
|
|||||||
import acpki
|
import acpki
|
||||||
import drtio_aux_controller
|
import drtio_aux_controller
|
||||||
import zynq_clocking
|
import zynq_clocking
|
||||||
from config import write_csr_file, write_mem_file, write_rustc_cfg_file
|
from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
|
||||||
|
|
||||||
class SMAClkinForward(Module):
|
class SMAClkinForward(Module):
|
||||||
def __init__(self, platform):
|
def __init__(self, platform):
|
||||||
@ -130,7 +130,7 @@ class ZC706(SoCCore):
|
|||||||
platform = zc706.Platform()
|
platform = zc706.Platform()
|
||||||
prepare_zc706_platform(platform)
|
prepare_zc706_platform(platform)
|
||||||
|
|
||||||
ident = self.__class__.__name__
|
ident = generate_ident(self.__class__.__name__)
|
||||||
if self.acpki:
|
if self.acpki:
|
||||||
ident = "acpki_" + ident
|
ident = "acpki_" + ident
|
||||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
||||||
@ -203,7 +203,7 @@ class _MasterBase(SoCCore):
|
|||||||
|
|
||||||
platform = zc706.Platform()
|
platform = zc706.Platform()
|
||||||
prepare_zc706_platform(platform)
|
prepare_zc706_platform(platform)
|
||||||
ident = self.__class__.__name__
|
ident = generate_ident(self.__class__.__name__)
|
||||||
if self.acpki:
|
if self.acpki:
|
||||||
ident = "acpki_" + ident
|
ident = "acpki_" + ident
|
||||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
||||||
@ -344,7 +344,7 @@ class _SatelliteBase(SoCCore):
|
|||||||
|
|
||||||
platform = zc706.Platform()
|
platform = zc706.Platform()
|
||||||
prepare_zc706_platform(platform)
|
prepare_zc706_platform(platform)
|
||||||
ident = self.__class__.__name__
|
ident = generate_ident(self.__class__.__name__)
|
||||||
if self.acpki:
|
if self.acpki:
|
||||||
ident = "acpki_" + ident
|
ident = "acpki_" + ident
|
||||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
||||||
|
@ -10,15 +10,11 @@ use io::Cursor;
|
|||||||
#[cfg(has_drtio)]
|
#[cfg(has_drtio)]
|
||||||
use ksupport::rpc;
|
use ksupport::rpc;
|
||||||
use ksupport::{kernel, resolve_channel_name};
|
use ksupport::{kernel, resolve_channel_name};
|
||||||
#[cfg(has_drtio)]
|
|
||||||
use libasync::delay;
|
|
||||||
use libasync::{smoltcp::{Sockets, TcpStream},
|
use libasync::{smoltcp::{Sockets, TcpStream},
|
||||||
task};
|
task};
|
||||||
use libboard_artiq::drtio_routing;
|
use libboard_artiq::drtio_routing;
|
||||||
#[cfg(feature = "target_kasli_soc")]
|
#[cfg(feature = "target_kasli_soc")]
|
||||||
use libboard_zynq::error_led::ErrorLED;
|
use libboard_zynq::error_led::ErrorLED;
|
||||||
#[cfg(has_drtio)]
|
|
||||||
use libboard_zynq::time::Milliseconds;
|
|
||||||
use libboard_zynq::{self as zynq,
|
use libboard_zynq::{self as zynq,
|
||||||
smoltcp::{self,
|
smoltcp::{self,
|
||||||
iface::{EthernetInterfaceBuilder, NeighborCache},
|
iface::{EthernetInterfaceBuilder, NeighborCache},
|
||||||
|
Loading…
Reference in New Issue
Block a user