forked from M-Labs/artiq-zynq
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cb10903899
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9bd07b0759
Author | SHA1 | Date |
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mwojcik | 9bd07b0759 | |
mwojcik | 4dae3d77ee |
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@ -61,13 +61,15 @@ class SMAClkinForward(Module):
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]
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]
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class GTP125BootstrapClock(Module):
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class GTPBootstrapClock(Module):
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def __init__(self, platform):
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def __init__(self, platform, freq=125e6):
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self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
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self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
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self.cd_bootstrap.clk.attr.add("keep")
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self.cd_bootstrap.clk.attr.add("keep")
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bootstrap_125 = platform.request("clk125_gtp")
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bootstrap_125 = platform.request("clk125_gtp")
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bootstrap_se = Signal()
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bootstrap_se = Signal()
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clk_out = Signal()
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platform.add_period_constraint(bootstrap_125.p, 8.0)
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platform.add_period_constraint(bootstrap_125.p, 8.0)
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self.specials += [
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self.specials += [
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Instance("IBUFDS_GTE2",
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Instance("IBUFDS_GTE2",
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@ -77,8 +79,30 @@ class GTP125BootstrapClock(Module):
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p_CLKCM_CFG="TRUE",
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3),
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p_CLKSWING_CFG=3),
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Instance("BUFG", i_I=bootstrap_se, o_O=self.cd_bootstrap.clk)
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Instance("BUFG", i_I=bootstrap_se, o_O=clk_out)
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]
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]
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if freq == 125e6:
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self.comb += self.cd_bootstrap.clk.eq(clk_out)
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elif freq == 100e6:
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pll_fb = Signal()
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pll_out = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_CLKIN1_PERIOD=8.0,
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i_CLKIN1=clk_out,
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i_CLKFBIN=pll_fb,
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o_CLKFBOUT=pll_fb,
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# VCO @ 1GHz
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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# 100MHz for bootstrap
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p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_out,
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),
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Instance("BUFG", i_I=pll_out, o_O=self.cd_bootstrap.clk)
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]
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else:
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raise ValueError("Bootstrap frequency must be 100 or 125MHz")
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class GenericStandalone(SoCCore):
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class GenericStandalone(SoCCore):
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@ -95,6 +119,7 @@ class GenericStandalone(SoCCore):
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules += SMAClkinForward(self.platform)
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self.submodules += SMAClkinForward(self.platform)
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@ -109,8 +134,7 @@ class GenericStandalone(SoCCore):
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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fix_serdes_timing_path(platform)
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, description["rtio_frequency"])
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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@ -203,7 +227,7 @@ class GenericMaster(SoCCore):
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gtx0 = self.gt_drtio.gtxs[0]
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.platform,
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self.ps7,
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self.ps7,
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@ -344,7 +368,7 @@ class GenericSatellite(SoCCore):
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gtx0 = self.gt_drtio.gtxs[0]
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.platform,
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self.ps7,
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self.ps7,
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@ -264,7 +264,10 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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{
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{
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let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
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let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
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match clk {
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match clk {
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RtioClock::Ext0_Bypass => si5324::bypass(i2c, SI5324_EXT_INPUT, timer).expect("cannot bypass Si5324"),
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RtioClock::Ext0_Bypass => {
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info!("bypassing the PLL for RTIO clock");
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si5324::bypass(i2c, SI5324_EXT_INPUT, timer).expect("cannot bypass Si5324")
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},
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_ => setup_si5324(i2c, timer, clk),
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_ => setup_si5324(i2c, timer, clk),
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}
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}
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}
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}
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