e31a31c4ff
master: drtioaux:
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- support async flag
- source in packets
- rerouting packets
2024-01-11 12:33:02 +08:00
6ca1719033
comms: fix compilation on standalone
2023-11-14 14:08:31 +08:00
aebc739c1e
add support for tar flashable (sub)kernels
2023-11-13 11:24:23 +08:00
e1b2c45813
kasli_soc & zc706: Fix GTX Clock Path during INIT
2023-11-07 18:55:08 +08:00
e6372b9766
zynq_clocking: Allow ext signal to set cur_clk csr
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- for example, current_clock csr can be connected to tx_init.done
2023-11-07 18:55:08 +08:00
07044752b6
zynq_clocking: add ext_async_rst to AsyncRstSYNCR
2023-11-07 18:55:08 +08:00
79fc5a7789
zynq_clocking: expose mmcm_locked for SYSCRG
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- mmcm_locked -> self.mmcm_locked
2023-11-07 18:55:08 +08:00
6c8346ca5f
subkernel: improve stability,
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fix exception on awaiting message
2023-11-02 16:58:34 +08:00
b76f634686
drtio: increase robustness for longer payloads
2023-11-02 14:48:52 +08:00
4a34777b97
refactor i2c, io_expander, task under the same cfg
2023-10-25 11:52:04 +08:00
43e4527392
fix kasli-soc demo compilation warning
2023-10-25 11:45:13 +08:00
0a3bfc9a61
subkernel: separate tags and data
2023-10-18 12:03:43 +08:00
d3fbfd75b0
Fix grabber build and warning
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-10-18 11:24:43 +08:00
b768d5648c
Add grabber module
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Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-10-16 14:35:20 +08:00
812aea33b3
rustfmt
2023-10-11 17:56:30 +08:00
136e24f597
kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1
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- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
2023-10-11 16:45:26 +08:00
a4d1be00c0
Firmware: Add drtio_eem.rs support
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- Port from Artiq repo
- Initialize the drtio_eem on main, rtio_clocking
- Driver for eem_transceiver
2023-10-10 11:22:05 +08:00
b15322b6ba
kasli_soc: Add support for shuttler on gateware
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- Port from artiq repo
- Add EEM_DRTIO gateware
2023-10-10 11:22:05 +08:00
8fd1306145
zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL
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- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
2023-10-10 11:21:34 +08:00
a28a819b18
add manifests target to PHONY
2023-10-09 18:29:53 +08:00
3f414278e2
cleanup
2023-10-09 18:28:20 +08:00
e5aafad60d
force cargo to use our copy of zynq-rs
2023-10-09 18:27:58 +08:00
b9a0bcabeb
ksupport: fix build on acpki variants
2023-10-09 17:10:45 +08:00
8eb359ee42
cargo fmt
2023-10-09 11:50:47 +08:00
7263862fd8
satellite: support optional args
2023-10-09 11:42:51 +08:00
29cc0a6e28
ddma/subkernel: fix wrong destination reported
2023-10-09 11:42:51 +08:00
616c40429e
satellite: process kernel requests more often
2023-10-09 11:42:51 +08:00
3ea8147966
subkernel: send async statuses when requested
2023-10-09 11:42:51 +08:00
cb79c12284
satellite: support subkernels
2023-10-09 11:42:51 +08:00
623cc7b79e
libkernel -> ksupport
2023-10-09 11:42:51 +08:00
49205eea17
satellite gateware: add kernel rtio to cri
2023-10-09 11:36:23 +08:00
6885c618b5
move kernel-related code to separate library
2023-10-09 11:36:23 +08:00
c696fd826f
master: support optional args
2023-10-09 10:35:47 +08:00
4b3c9a3d08
rtio_mgt: remove support for async messages
2023-10-09 10:35:47 +08:00
779aea7c6a
check subkernel exceptions only when awaited
2023-10-09 10:35:03 +08:00
6785ca2c85
subkernel: port master support
2023-10-09 10:35:03 +08:00
656cbf4546
kasli_soc: use sed_lanes value from HW description
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https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
2023-10-06 15:37:56 +01:00
ecd4ca333c
rtio_clocking: inform the user if PLL is bypassed
2023-10-06 16:27:25 +08:00
ae3099dd8e
kasli_soc: support 100MHz clock
2023-10-06 16:27:25 +08:00
49810da188
runtime: wait longer for PLL lock
2023-10-05 12:17:43 +08:00
e451598a06
satman: fix dma reporting wrong destination
2023-09-22 10:29:48 +08:00
f4ceca464f
drtio: change async messages to sync
2023-09-21 14:18:25 +08:00
f3dcd53086
firmware: fix zc706 compilation warnings
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Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-09-11 15:21:56 +08:00
b3856e879b
refactor write_rustc_cfg_file()
2023-09-11 11:48:19 +08:00
1ccae0d442
consolidate all write..file() into config.py
2023-09-11 11:48:19 +08:00
2c19f4ac31
replace rustc_cfg[ ] & change write_rustc_cfg_file
2023-09-11 11:48:19 +08:00
85ecff2cc1
cargo: update zynq-rs
2023-09-07 19:01:36 +08:00
3a305c8cac
Revert "cargo: update dependencies"
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This reverts commit 38b0799bb0
2023-09-07 19:00:16 +08:00
38b0799bb0
cargo: update dependencies
2023-09-07 18:54:30 +08:00
615f2e3d37
remove misleading 'Actively' from docs at main.rs
2023-09-06 10:53:26 +08:00
