forked from M-Labs/artiq-zynq
dma: use const initializer for manager
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886582869c
commit
e64f59723c
@ -15,7 +15,6 @@ use crate::eh_artiq;
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use super::{
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use super::{
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api::resolve,
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api::resolve,
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rpc::rpc_send_async,
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rpc::rpc_send_async,
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dma::init_dma,
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CHANNEL_0TO1, CHANNEL_1TO0,
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CHANNEL_0TO1, CHANNEL_1TO0,
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KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
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KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0,
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KERNEL_IMAGE,
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KERNEL_IMAGE,
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@ -126,9 +125,6 @@ pub fn main_core1() {
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enable_fpu();
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enable_fpu();
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debug!("FPU enabled on Core1");
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debug!("FPU enabled on Core1");
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init_dma();
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debug!("Init DMA!");
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let mut core1_tx = None;
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let mut core1_tx = None;
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while core1_tx.is_none() {
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while core1_tx.is_none() {
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core1_tx = CHANNEL_1TO0.lock().take();
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core1_tx = CHANNEL_1TO0.lock().take();
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@ -46,7 +46,7 @@ pub struct Manager {
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// Copied from https://github.com/m-labs/artiq/blob/master/artiq/firmware/runtime/rtio_dma.rs
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// Copied from https://github.com/m-labs/artiq/blob/master/artiq/firmware/runtime/rtio_dma.rs
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// basically without modification except removing some warnings.
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// basically without modification except removing some warnings.
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impl Manager {
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impl Manager {
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pub fn new() -> Manager {
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pub const fn new() -> Manager {
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Manager {
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Manager {
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entries: BTreeMap::new(),
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entries: BTreeMap::new(),
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recording_name: String::new(),
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recording_name: String::new(),
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@ -106,7 +106,7 @@ impl Manager {
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}
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}
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static mut DMA_MANAGER: Option<Manager> = None;
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static mut DMA_MANAGER: Manager = Manager::new();
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#[repr(C)]
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#[repr(C)]
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pub struct DmaTrace {
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pub struct DmaTrace {
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@ -114,16 +114,9 @@ pub struct DmaTrace {
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address: i32,
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address: i32,
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}
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}
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pub fn init_dma() {
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unsafe {
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DMA_MANAGER = Some(Manager::new());
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}
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}
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fn dma_record_flush() {
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fn dma_record_flush() {
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unsafe {
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unsafe {
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let manager = DMA_MANAGER.as_mut().unwrap();
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DMA_MANAGER.record_append(&DMA_RECORDER.buffer[..DMA_RECORDER.data_len]);
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manager.record_append(&DMA_RECORDER.buffer[..DMA_RECORDER.data_len]);
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DMA_RECORDER.data_len = 0;
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DMA_RECORDER.data_len = 0;
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}
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}
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}
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}
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@ -143,8 +136,7 @@ pub extern fn dma_record_start(name: CSlice<u8>) {
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dma_record_output_wide as *const ()).unwrap();
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dma_record_output_wide as *const ()).unwrap();
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DMA_RECORDER.active = true;
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DMA_RECORDER.active = true;
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let manager = DMA_MANAGER.as_mut().unwrap();
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DMA_MANAGER.record_start(name);
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manager.record_start(name);
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}
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}
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}
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}
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@ -163,8 +155,7 @@ pub extern fn dma_record_stop(duration: i64) {
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rtio::output_wide as *const ()).unwrap();
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rtio::output_wide as *const ()).unwrap();
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DMA_RECORDER.active = false;
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DMA_RECORDER.active = false;
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let manager = DMA_MANAGER.as_mut().unwrap();
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DMA_MANAGER.record_stop(duration as u64);
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manager.record_stop(duration as u64);
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}
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}
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}
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}
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@ -238,23 +229,21 @@ pub extern fn dma_record_output_wide(target: i32, words: CSlice<i32>) {
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pub extern fn dma_erase(name: CSlice<u8>) {
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pub extern fn dma_erase(name: CSlice<u8>) {
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let name = str::from_utf8(name.as_ref()).unwrap();
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let name = str::from_utf8(name.as_ref()).unwrap();
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let manager = unsafe {
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unsafe {
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DMA_MANAGER.as_mut().unwrap()
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DMA_MANAGER.erase(name);
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};
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};
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manager.erase(name);
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}
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}
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pub extern fn dma_retrieve(name: CSlice<u8>) -> DmaTrace {
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pub extern fn dma_retrieve(name: CSlice<u8>) -> DmaTrace {
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let name = str::from_utf8(name.as_ref()).unwrap();
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let name = str::from_utf8(name.as_ref()).unwrap();
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let manager = unsafe {
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let (trace, duration) = unsafe {
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DMA_MANAGER.as_mut().unwrap()
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DMA_MANAGER.with_trace(name, |trace, duration| (trace.map(|v| {
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};
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let (trace, duration) = manager.with_trace(name, |trace, duration| (trace.map(|v| {
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dcci_slice(v);
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dcci_slice(v);
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dsb();
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dsb();
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v.as_ptr()
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v.as_ptr()
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}), duration));
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}), duration))
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};
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match trace {
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match trace {
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Some(ptr) => Ok(DmaTrace {
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Some(ptr) => Ok(DmaTrace {
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address: ptr as i32,
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address: ptr as i32,
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@ -4,6 +4,7 @@
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#![feature(alloc_error_handler)]
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#![feature(alloc_error_handler)]
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#![feature(panic_info_message)]
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#![feature(panic_info_message)]
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#![feature(c_variadic)]
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#![feature(c_variadic)]
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#![feature(const_btree_new)]
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extern crate alloc;
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extern crate alloc;
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