From 805beeacafd985fd71bf328a6d640ad0df6fc84c Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 29 Nov 2024 16:08:56 +0800 Subject: [PATCH] kasli_soc: separate master drtio memory from rest --- src/gateware/kasli_soc.py | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 98d6f41..26d4300 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -8,7 +8,9 @@ from migen.build.generic_platform import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.cdc import MultiReg from migen_axi.integration.soc_core import SoCCore +from migen_axi.interconnect import axi, axi2csr from migen_axi.platforms import kasli_soc +from misoc.interconnect import csr_bus from misoc.interconnect.csr import * from misoc.cores import virtual_leds @@ -308,6 +310,14 @@ class GenericMaster(SoCCore): self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) + self.submodules.drtio_axi2csr = axi2csr.AXI2CSR( + bus_csr=csr_bus.Interface(self.csr_data_width, self.csr_address_width), + bus_axi=axi.Interface.like(self.ps7.m_axi_gp0)) + + self.register_mem("drtio_csr", self.mem_map["axi"], + 4 * 2**(self.csr_address_width), + self.drtio_axi2csr.bus) + self.drtio_csr_group = [] self.drtioaux_csr_group = [] self.drtioaux_memory_group = [] @@ -332,9 +342,9 @@ class GenericMaster(SoCCore): self.csr_devices.append(coreaux_name) size = coreaux.get_mem_size() - memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size) - self.axi2csr.register_port(coreaux.get_rx_port(), size) - self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2) + memory_address = self.drtio_axi2csr.register_port(coreaux.get_tx_port(), size) + self.drtio_axi2csr.register_port(coreaux.get_rx_port(), size) + self.add_memory_region(memory_name, self.mem_map["axi"] + memory_address, size * 2) self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO_ROUTING"] = None