mwojcik/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Issues Pull Requests Projects Releases Wiki Activity

kernel: added core1 instruction cache flush

Browse Source
This commit is contained in:
pca006132 2020-07-10 17:17:52 +08:00
parent 68d27ca2ee
commit 7aec419ed6
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/runtime/src/kernel/core1.rs
View File

@ -5,7 +5,7 @@ use alloc::borrow::ToOwned;
use log::{debug, info, error};
use cslice::CSlice;
use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel};
use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
use dyld::{self, Library};
use crate::eh_artiq;
use super::{
@ -92,6 +92,7 @@ impl KernelImage {
// Flush data cache entries for the image in DDR, including
// Memory/Instruction Synchronization Barriers
dcci_slice(self.library.image.data);
iciallu();
(mem::transmute::<u32, fn()>(self.__modinit__))();