forked from M-Labs/artiq-zynq
kasli soc: refactor to use wrpll from artiq
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1fbaacfc43
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377f8779a0
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@ -20,13 +20,13 @@ from artiq.gateware.drtio.transceiver import gtx_7series, eem_serdes
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.gateware.drtio import *
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from artiq.gateware.wrpll import wrpll
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import dma
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import dma
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import analyzer
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import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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import zynq_clocking
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import zynq_clocking
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import wrpll
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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eem_iostandard_dict = {
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@ -146,7 +146,7 @@ class GenericStandalone(SoCCore):
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self.crg.cd_sys = self.sys_crg.cd_sys
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self.crg.cd_sys = self.sys_crg.cd_sys
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if with_wrpll:
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if with_wrpll:
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll_refclk = wrpll.FrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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cd_ref=self.wrpll_refclk.cd_ref,
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@ -275,7 +275,7 @@ class GenericMaster(SoCCore):
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clk_synth_se = Signal()
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll_refclk = wrpll.FrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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cd_ref=self.wrpll_refclk.cd_ref,
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