forked from M-Labs/artiq-zynq
Firmware: Satman WRPLL
satman: drive CLK_SEL to true when si549 is used satman : add main & helper si549 setup satman : add WRPLL select_recovered_clock si549: add tag collector to process gtx & main tags si549: add frequency counter to set BASE_ADPLL si549: add set_adpll for main & helper PLL si549: add main & helper PLL FIQ & si549: replace dummy with a custom handler for gtx & main tags ISR
This commit is contained in:
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a1d80fb93b
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@ -25,7 +25,7 @@ void = { version = "1", default-features = false }
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io = { path = "../libio", features = ["byteorder"] }
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libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }
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libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core", "dummy_fiq_handler"] }
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libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
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libregister = { path = "@@ZYNQ_RS@@/libregister" }
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libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn"] }
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libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
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22
src/libboard_artiq/src/fiq.rs
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22
src/libboard_artiq/src/fiq.rs
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@ -0,0 +1,22 @@
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use libboard_zynq::{println, stdio};
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use libcortex_a9::{interrupt_handler, regs::MPIDR};
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use libregister::RegisterR;
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#[cfg(has_si549)]
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use crate::si549;
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interrupt_handler!(FIQ, fiq, __irq_stack0_start, __irq_stack1_start, {
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match MPIDR.read().cpu_id() {
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0 => {
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// nFIQ is driven directly and bypass GIC
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#[cfg(has_si549)]
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si549::wrpll::interrupt_handler();
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return;
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}
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_ => {}
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};
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stdio::drop_uart();
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println!("FIQ");
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loop {}
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});
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@ -1,5 +1,7 @@
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#![no_std]
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#![feature(never_type)]
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#![feature(naked_functions)]
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#![feature(asm)]
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extern crate core_io;
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extern crate crc;
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@ -19,6 +21,7 @@ pub mod drtioaux;
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#[cfg(has_drtio)]
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pub mod drtioaux_async;
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pub mod drtioaux_proto;
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pub mod fiq;
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#[cfg(all(feature = "target_kasli_soc", has_drtio))]
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pub mod io_expander;
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pub mod logger;
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@ -324,3 +324,219 @@ fn set_adpll(dcxo: i2c::DCXO, adpll: i32) -> Result<(), &'static str> {
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Ok(())
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}
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#[cfg(has_wrpll)]
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pub mod wrpll {
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use super::*;
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const BEATING_PERIOD: i32 = 0x8000;
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const BEATING_HALFPERIOD: i32 = 0x4000;
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const COUNTER_WIDTH: u32 = 24;
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const DIV_WIDTH: u32 = 2;
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const KP: i32 = 6;
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const KI: i32 = 2;
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// 4 ppm capture range
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const ADPLL_LIM: i32 = (4.0 / 0.0001164) as i32;
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static mut BASE_ADPLL: i32 = 0;
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static mut H_LAST_ADPLL: i32 = 0;
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static mut LAST_PERIOD_ERR: i32 = 0;
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static mut M_LAST_ADPLL: i32 = 0;
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static mut LAST_PHASE_ERR: i32 = 0;
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#[derive(Clone, Copy)]
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pub enum ISR {
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RefTag,
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MainTag,
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}
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mod tag_collector {
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use super::*;
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static mut REF_TAG: u32 = 0;
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static mut REF_TAG_READY: bool = false;
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static mut MAIN_TAG: u32 = 0;
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static mut MAIN_TAG_READY: bool = false;
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pub fn reset() {
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clear_phase_diff_ready();
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unsafe {
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REF_TAG = 0;
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MAIN_TAG = 0;
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}
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}
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pub fn clear_phase_diff_ready() {
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unsafe {
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REF_TAG_READY = false;
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MAIN_TAG_READY = false;
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}
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}
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pub fn collect_tags(interrupt: ISR) {
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match interrupt {
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ISR::RefTag => unsafe {
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REF_TAG = csr::wrpll::ref_tag_read();
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REF_TAG_READY = true;
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},
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ISR::MainTag => unsafe {
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MAIN_TAG = csr::wrpll::main_tag_read();
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MAIN_TAG_READY = true;
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},
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}
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}
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pub fn phase_diff_ready() -> bool {
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unsafe { REF_TAG_READY && MAIN_TAG_READY }
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}
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pub fn get_period_error() -> i32 {
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// n * BEATING_PERIOD - REF_TAG(n) mod BEATING_PERIOD
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let mut period_error = unsafe { REF_TAG.overflowing_neg().0.rem_euclid(BEATING_PERIOD as u32) as i32 };
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// mapping tags from [0, 2π] -> [-π, π]
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if period_error > BEATING_HALFPERIOD {
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period_error -= BEATING_PERIOD
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}
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period_error
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}
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pub fn get_phase_error() -> i32 {
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// MAIN_TAG(n) - REF_TAG(n) mod BEATING_PERIOD
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let mut phase_error =
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unsafe { MAIN_TAG.overflowing_sub(REF_TAG).0.rem_euclid(BEATING_PERIOD as u32) as i32 };
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// mapping tags from [0, 2π] -> [-π, π]
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if phase_error > BEATING_HALFPERIOD {
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phase_error -= BEATING_PERIOD
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}
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phase_error
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}
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}
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fn set_isr(en: bool) {
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let val = if en { 1 } else { 0 };
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unsafe {
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csr::wrpll::ref_tag_ev_enable_write(val);
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csr::wrpll::main_tag_ev_enable_write(val);
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}
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}
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fn set_base_adpll() -> Result<(), &'static str> {
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let count2adpll =
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|error: i32| ((error as f64 * 1e6) / (0.0001164 * (1 << (COUNTER_WIDTH - DIV_WIDTH)) as f64)) as i32;
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let (ref_count, main_count) = get_freq_counts();
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unsafe {
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BASE_ADPLL = count2adpll(ref_count as i32 - main_count as i32);
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set_adpll(i2c::DCXO::Main, BASE_ADPLL)?;
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set_adpll(i2c::DCXO::Helper, BASE_ADPLL)?;
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}
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Ok(())
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}
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fn get_freq_counts() -> (u32, u32) {
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unsafe {
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csr::wrpll::frequency_counter_update_write(1);
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while csr::wrpll::frequency_counter_busy_read() == 1 {}
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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let ref_count = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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let ref_count = csr::wrpll::frequency_counter_counter_ref_read();
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let main_count = csr::wrpll::frequency_counter_counter_sys_read();
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(ref_count, main_count)
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}
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}
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fn reset_plls(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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unsafe {
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H_LAST_ADPLL = 0;
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LAST_PERIOD_ERR = 0;
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M_LAST_ADPLL = 0;
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LAST_PHASE_ERR = 0;
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}
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set_adpll(i2c::DCXO::Main, 0)?;
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set_adpll(i2c::DCXO::Helper, 0)?;
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// wait for adpll to transfer and DCXO to settle
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timer.delay_us(200);
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Ok(())
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}
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fn clear_pending(interrupt: ISR) {
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match interrupt {
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ISR::RefTag => unsafe { csr::wrpll::ref_tag_ev_pending_write(1) },
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ISR::MainTag => unsafe { csr::wrpll::main_tag_ev_pending_write(1) },
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};
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}
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fn is_pending(interrupt: ISR) -> bool {
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match interrupt {
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ISR::RefTag => unsafe { csr::wrpll::ref_tag_ev_pending_read() == 1 },
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ISR::MainTag => unsafe { csr::wrpll::main_tag_ev_pending_read() == 1 },
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}
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}
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pub fn interrupt_handler() {
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if is_pending(ISR::RefTag) {
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tag_collector::collect_tags(ISR::RefTag);
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clear_pending(ISR::RefTag);
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helper_pll().expect("failed to run helper DCXO PLL");
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}
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if is_pending(ISR::MainTag) {
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tag_collector::collect_tags(ISR::MainTag);
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clear_pending(ISR::MainTag);
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}
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if tag_collector::phase_diff_ready() {
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main_pll().expect("failed to run main DCXO PLL");
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tag_collector::clear_phase_diff_ready();
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}
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}
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fn helper_pll() -> Result<(), &'static str> {
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let period_err = tag_collector::get_period_error();
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unsafe {
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// Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
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let adpll = (H_LAST_ADPLL + (KP + KI) * period_err - KP * LAST_PERIOD_ERR).clamp(-ADPLL_LIM, ADPLL_LIM);
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set_adpll(i2c::DCXO::Helper, BASE_ADPLL + adpll)?;
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H_LAST_ADPLL = adpll;
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LAST_PERIOD_ERR = period_err;
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};
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Ok(())
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}
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fn main_pll() -> Result<(), &'static str> {
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let phase_err = tag_collector::get_phase_error();
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unsafe {
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// Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
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let adpll = (M_LAST_ADPLL + (KP + KI) * phase_err - KP * LAST_PHASE_ERR).clamp(-ADPLL_LIM, ADPLL_LIM);
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set_adpll(i2c::DCXO::Main, BASE_ADPLL + adpll)?;
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M_LAST_ADPLL = adpll;
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LAST_PHASE_ERR = phase_err;
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};
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Ok(())
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}
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pub fn select_recovered_clock(rc: bool, timer: &mut GlobalTimer) {
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set_isr(false);
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if rc {
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tag_collector::reset();
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reset_plls(timer).expect("failed to reset main and helper PLL");
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// get within capture range
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set_base_adpll().expect("failed to set base adpll");
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// clear gateware pending flag
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clear_pending(ISR::RefTag);
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clear_pending(ISR::MainTag);
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// use nFIQ to avoid IRQ being disabled by mutex lock and mess up PLL
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set_isr(true);
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info!("WRPLL interrupt enabled");
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}
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}
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}
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@ -29,6 +29,8 @@ use libboard_artiq::grabber;
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use libboard_artiq::io_expander;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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#[cfg(has_si549)]
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use libboard_artiq::si549;
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use libboard_artiq::{drtio_routing, drtioaux,
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drtioaux_proto::{MASTER_PAYLOAD_MAX_SIZE, SAT_PAYLOAD_MAX_SIZE},
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identifier_read, logger,
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@ -828,6 +830,36 @@ const SI5324_SETTINGS: si5324::FrequencySettings = si5324::FrequencySettings {
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crystal_as_ckin2: true,
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};
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#[cfg(all(has_si549, rtio_frequency = "125.0"))]
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const SI549_SETTINGS: si549::FrequencySetting = si549::FrequencySetting {
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main: si549::DividerConfig {
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hsdiv: 0x058,
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lsdiv: 0,
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fbdiv: 0x04815791F25,
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},
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helper: si549::DividerConfig {
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// 125MHz*32767/32768
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hsdiv: 0x058,
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lsdiv: 0,
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fbdiv: 0x04814E8F442,
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},
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};
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#[cfg(all(has_si549, rtio_frequency = "100.0"))]
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const SI549_SETTINGS: si549::FrequencySetting = si549::FrequencySetting {
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main: si549::DividerConfig {
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hsdiv: 0x06C,
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lsdiv: 0,
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fbdiv: 0x046C5F49797,
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},
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helper: si549::DividerConfig {
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// 100MHz*32767/32768
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hsdiv: 0x06C,
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lsdiv: 0,
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fbdiv: 0x046C5670BBD,
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},
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};
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static mut LOG_BUFFER: [u8; 1 << 17] = [0; 1 << 17];
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#[no_mangle]
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@ -864,6 +896,11 @@ pub extern "C" fn main_core0() -> i32 {
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io_expander1
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.init(&mut i2c)
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.expect("I2C I/O expander #1 initialization failed");
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// Drive CLK_SEL to true
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#[cfg(has_si549)]
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io_expander0.set(1, 7, true);
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// Drive TX_DISABLE to false on SFP0..3
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io_expander0.set(0, 1, false);
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io_expander1.set(0, 1, false);
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@ -875,6 +912,8 @@ pub extern "C" fn main_core0() -> i32 {
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#[cfg(has_si5324)]
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si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
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#[cfg(has_si549)]
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si549::main_setup(&mut timer, &SI549_SETTINGS).expect("cannot initialize main Si549");
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timer.delay_us(100_000);
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info!("Switching SYS clocks...");
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@ -892,6 +931,8 @@ pub extern "C" fn main_core0() -> i32 {
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unsafe {
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csr::gt_drtio::txenable_write(0xffffffffu32 as _);
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}
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#[cfg(has_si549)]
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si549::helper_setup(&mut timer, &SI549_SETTINGS).expect("cannot initialize helper Si549");
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#[cfg(has_drtio_routing)]
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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@ -937,6 +978,9 @@ pub extern "C" fn main_core0() -> i32 {
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si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
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}
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#[cfg(has_wrpll)]
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si549::wrpll::select_recovered_clock(true, &mut timer);
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// Various managers created here, so when link is dropped, all DMA traces
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// are cleared out for a clean slate on subsequent connections,
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// without a manual intervention.
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@ -1034,6 +1078,8 @@ pub extern "C" fn main_core0() -> i32 {
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info!("uplink is down, switching to local oscillator clock");
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#[cfg(has_siphaser)]
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si5324::siphaser::select_recovered_clock(&mut i2c, false, &mut timer).expect("failed to switch clocks");
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#[cfg(has_wrpll)]
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si549::wrpll::select_recovered_clock(false, &mut timer);
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}
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}
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