From 0b0ca8de49efa8c214b7dde685a4ba23923539f9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 15 Jul 2020 23:11:19 +0800 Subject: [PATCH] analyzer: drive wid and wstrb --- src/gateware/analyzer.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gateware/analyzer.py b/src/gateware/analyzer.py index 7a8f4d1..3dd6662 100644 --- a/src/gateware/analyzer.py +++ b/src/gateware/analyzer.py @@ -52,9 +52,11 @@ class AXIDMAWriter(Module, AutoCSR): ] self.comb += [ + membus.w.id.eq(0), membus.w.valid.eq(self.sink.stb), self.sink.ack.eq(membus.w.ready), - membus.w.data.eq(self.sink.data) + membus.w.data.eq(self.sink.data), + membus.w.strb.eq(2**(dw//8)-1), ] beat_count = Signal(max=burst_length) self.sync += [