• Joined on 2023-07-24
Loading Heatmap…

morgan pushed to DDMTD at morgan/artiq-zynq

2024-04-26 12:35:51 +08:00

morgan created branch DDMTD in morgan/artiq-zynq

2024-04-26 12:34:22 +08:00

morgan pushed to DDMTD at morgan/artiq-zynq

2024-04-26 12:34:22 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Force pushed changelog - gateware - doc clenaup - increase blind period to 400 to improve lock stability for satman - si549 - strobe now use CSR - the nack…

2024-04-12 16:46:36 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-04-12 16:45:31 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-04-09 17:34:28 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-04-09 17:33:39 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Yes, that will also save time. The select_recovered_clock(true) is called directly after [drtiosat_link_rx_up](https://git.m-labs.hk/M-Labs/artiq-zynq/src/commit/1f7c53b8d0dfab4a0194e6a860e57bb17e…

2024-03-26 15:56:09 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

it's waiting for the gtx_cdr, sometimes the cdr is not locked/stable yet and the frequency counter will read the wrong value.

2024-03-26 15:37:44 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Yes, will change it to `static mut`

2024-03-26 15:36:39 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Force push changelog - kasli soc - revert the `ClockSynthesis` refactor - add `clk_synth`, `IBUFGDS` & `period constraint` for master and satellite - Testing - master & standalone:…

2024-03-26 13:27:14 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-03-26 13:23:24 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-03-26 12:10:48 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Force push changelog - cleanup some of the commit message - Gateware: - rename GTX_CDR -> GT_CDR - Firmware: - si549: cfg rename GTX_CDR -> GT_CDR - wrpll_refclk: remove timer…

2024-03-19 12:55:33 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-03-19 12:45:48 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-03-19 11:39:01 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Force push changelog - Flake - update artiq for the `enable_wrpll` json field - Gateware - replace the --use-wrpll arg with the `enable_wrpll` field in json - add SkewTester -…

2024-03-19 11:11:10 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-03-19 11:08:50 +08:00

morgan pushed to WRPLL at morgan/artiq-zynq

2024-03-19 11:05:51 +08:00

morgan commented on pull request M-Labs/artiq-zynq#282

Kasli-soc: add WRPLL clock recovery

Force push to rebase, cleanup and add support for runtime wrpll. Internal 150Mhz si549 and PLL bypass mode are not supported. ## Changelog - Gateware - ddmtd & wrpll - refactor to…

2024-03-11 15:05:31 +08:00