forked from M-Labs/zynq-rs
1
0
Fork 0
Commit Graph

19 Commits

Author SHA1 Message Date
Astro b8818863c4 read clocks 2019-08-17 03:20:04 +02:00
Astro 1f9ad5ff62 delint 2019-08-11 00:56:54 +02:00
Astro 54d0f3583d eth: fix io configuration
phy detection now works
2019-06-18 23:10:35 +02:00
Astro b9ca9324f0 eth: fix initialization 2019-06-04 23:48:33 +02:00
Astro acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
Astro c0610ad66a slcr: init gem* rclk/clk 2019-05-30 02:26:19 +02:00
Astro ee7ae7f7cc slcr: add soft_rst() 2019-05-30 00:24:51 +02:00
Astro b3da0e4c93 slcr: define all mio_pin regs, typed io_type 2019-05-25 02:34:58 +02:00
Astro 179c617904 add register_bits_typed! macro 2019-05-23 18:29:05 +02:00
Astro 785e726661 RegisterW/RegisterRW: required &mut self for safety 2019-05-23 18:01:18 +02:00
Astro 62ca26fa71 slcr: abstract with RegisterBlock 2019-05-23 17:52:06 +02:00
Astro 43b6d3acd0 uart: wait for reset 2019-05-21 02:53:59 +02:00
Astro 47ec0116a9 use uart1 with more configuration 2019-05-21 01:30:54 +02:00
Astro 5d02fe5c95 slcr: with_slcr() for unlock/lock 2019-05-21 01:30:17 +02:00
Astro 351d18c10f add register_at! macro 2019-05-20 23:01:50 +02:00
Astro ca9b10dce8 refactor regs macros for RO/WO/RW access 2019-05-07 00:32:45 +02:00
Astro fdc6c38de6 enable_uart0(): add srcsel 2019-05-07 00:01:43 +02:00
Astro 55957eea09 regs macros 2019-05-06 23:56:53 +02:00
Astro 9b414e2408 PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00