9550fe0687
Remove ecall and *ret instructions from riscv::asm
2018-12-18 23:58:50 +03:00
8776d30d3b
add S-Mode registers
...
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
2018-11-09 22:42:46 +08:00
9dc7b40fdd
impl sfence_vma & sfence_vma_all
2018-11-09 22:27:19 +08:00
4e16dd85ed
Merge #10
...
10: these raw instructions are unsafe r=dvc94ch a=strake
`wfi` is safe, but the rest are not. Let's make them all unsafe until we have a better idea — the return types are wrong anyhow.
Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
2018-08-19 17:02:05 +00:00
591b7df808
Merge #9
...
9: use `NonZeroUsize` where appropriate r=dvc94ch a=strake
Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
2018-08-19 11:12:24 +00:00
8e0faa9182
these raw instructions are unsafe
2018-08-18 10:26:59 -08:00
5a88960ee0
use `NonZeroUsize` where appropriate
2018-08-18 10:15:10 -08:00
ecc69bda00
mepc is word-size
2018-08-18 10:10:08 -08:00
6769ac9262
fix target_arch conditionals to match "riscv32" and "riscv64"
...
In the original riscv-rust fork the target arch was simply named
"riscv", but RISC-V support landed in Rust with "riscv32" as the arch
name instead.
Include "riscv64" optimistically for future-proofing.
2018-08-06 08:41:45 +10:00
8597f1c32d
Fix typo in register/misa.rs
2018-04-02 08:17:23 +02:00
45364b26a8
Add mepc register.
2018-03-30 12:14:27 +02:00
cd5200c5fa
Fix mstatus register value.
2018-03-29 15:37:49 +02:00
7db0e71060
New api.
2018-03-27 20:17:44 +02:00
179df42984
Remove inline(always).
2018-03-24 19:27:00 +01:00
21bfaf49ae
mcause is read-only.
2017-11-21 09:52:15 +01:00
bb41b209a6
Read bits only once.
2017-11-20 14:14:01 +01:00
467327cb15
Allow compiling on x86_64 for publishing.
2017-11-18 08:46:19 +01:00
e864581828
Initial commit.
2017-09-19 16:23:35 +02:00
Vadim Kaushan
WangRunji
bors[bot]
M Farkas-Dyck
Dan Callaghan
Jakob Weisblat
David Craven