Sean Cross
c5fbc0cc82
asm: use llvm_asm! macro()
...
This has been adjusted as part of the drive to stabilize the asm!()
macro.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-08-04 17:18:10 +08:00
Vadim Kaushan
e21ce5249f
Remove write functions for read-only registers
2020-06-14 14:45:17 +03:00
Vadim Kaushan
426fc067b4
Allow unused macros
2020-06-14 14:45:02 +03:00
Vadim Kaushan
7ce847ee3c
Fix register docs
2020-06-14 14:44:16 +03:00
Vadim Kaushan
11e7118729
Remove all the RISC-V standard registers
2020-06-14 14:20:38 +03:00
Sean Cross
fd54453416
register: add vexriscv-specific registers
...
Vexriscv in its normal configuration has its own registers for things
such as machine interrupts and system interrupts. Add wrappers for
these registers.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-08 17:22:16 +08:00
Gui Andrade
7a9aa062a0
Allow writing directly to satp register
2019-10-08 18:10:38 -07:00
Gui Andrade
95c52341c4
mip: Add set/clear functions for bits
2019-10-08 17:57:29 -07:00
Ales Katona
8840aee369
ucause only as readable bits
2019-08-31 17:32:43 -06:00
Ales Katona
e1232ed680
clean up formatting
2019-08-31 16:12:39 -06:00
Ales Katona
cdf6a33665
remove XS and FS from ustatus
2019-08-31 16:10:56 -06:00
Ales Katona
13831f7a80
revert scause specific trap/exceptions
2019-08-31 16:09:47 -06:00
Ales Katona
f443bcf698
remove invalid comment
2019-08-28 09:26:02 -06:00
Ales Katona
30555e4d79
fix typos in asm calls
2019-08-27 09:47:57 -06:00
Ales Katona
49446ad869
fix ustatus doc typos
2019-08-27 09:46:14 -06:00
Ales Katona
2180ef44d5
add user trap setup and handling registers
2019-08-27 09:40:47 -06:00
Vadim Kaushan
31f4127702
Add PMP CSRs
2019-06-26 11:25:45 +03:00
Vadim Kaushan
f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs
2019-06-26 00:51:37 +03:00
Vadim Kaushan
298a8b6f6e
Provide write() for mepc
2019-06-25 23:48:47 +03:00
Vadim Kaushan
7a8d3d1f6c
Implement mscratch and mtval registers
2019-06-25 23:48:27 +03:00
Vadim Kaushan
00367d4fd2
Add sections to the registers module
2019-06-25 23:34:47 +03:00
Vadim Kaushan
ac2ac6756b
Derive useful traits for enums
2019-06-25 23:32:51 +03:00
Vadim Kaushan
cf9008492a
Add marchid, mhartid and mimpid registers
2019-04-29 10:43:51 +02:00
Vadim Kaushan
ca797a35d8
Fix Misa::has_extension()
2019-04-01 19:58:40 +03:00
Vadim Kaushan
5baba0cb32
Add write function for sstatus register
2019-03-28 18:56:49 +03:00
Vadim Kaushan
9bb3b5803c
Refactoring: use set_bits() in set_fs function
2019-03-28 17:59:07 +03:00
Vadim Kaushan
5ef90e3189
Fix set_spp and set_mpp functions
2019-03-28 17:57:40 +03:00
Vadim Kaushan
6a2bdbf38d
Refactoring
2019-03-18 18:25:16 +03:00
Vadim Kaushan
4fb81f4860
Add FS and XS fields of mstatus
2019-03-18 18:14:00 +03:00
Vadim Kaushan
4ad2150a24
Add fcsr register
2019-03-17 19:06:29 +03:00
Vadim Kaushan
925c496949
Read composite CSRs as one 64-bit value
2019-03-01 17:46:35 +03:00
Vadim Kaushan
b665adeb95
Refactoring: use get_bit() instead of shifts
2019-03-01 17:10:45 +03:00
Andy Russell
8cbb3878e5
move doc comments inside macro invocations
2019-02-19 15:19:02 -05:00
Vadim Kaushan
ac1cba597a
Fix RISC-V name
...
https://riscv.org/risc-v-trademark-usage/
2019-01-24 17:19:32 +03:00
Vadim Kaushan
061579f97e
Call external functions when inline-asm is not set
2019-01-23 01:29:54 +03:00
Vadim Kaushan
41378757c0
Do not require const-fn and asm features
2019-01-23 01:29:54 +03:00
Vadim Kaushan
3652547073
Simplify #[cfg()] predicate expressions
2019-01-23 01:29:54 +03:00
Vadim Kaushan
52ad774fc1
Remove useless cfg_attr
2018-12-21 23:01:25 +01:00
Vadim Kaushan
921aa2bbec
Refactoring: use new macros for M-mode CSRs
2018-12-21 22:49:23 +01:00
WangRunji
8776d30d3b
add S-Mode registers
...
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
2018-11-09 22:42:46 +08:00
bors[bot]
591b7df808
Merge #9
...
9: use `NonZeroUsize` where appropriate r=dvc94ch a=strake
Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
2018-08-19 11:12:24 +00:00
M Farkas-Dyck
5a88960ee0
use `NonZeroUsize` where appropriate
2018-08-18 10:15:10 -08:00
M Farkas-Dyck
ecc69bda00
mepc is word-size
2018-08-18 10:10:08 -08:00
Dan Callaghan
6769ac9262
fix target_arch conditionals to match "riscv32" and "riscv64"
...
In the original riscv-rust fork the target arch was simply named
"riscv", but RISC-V support landed in Rust with "riscv32" as the arch
name instead.
Include "riscv64" optimistically for future-proofing.
2018-08-06 08:41:45 +10:00
Jakob Weisblat
8597f1c32d
Fix typo in register/misa.rs
2018-04-02 08:17:23 +02:00
David Craven
45364b26a8
Add mepc register.
2018-03-30 12:14:27 +02:00
David Craven
cd5200c5fa
Fix mstatus register value.
2018-03-29 15:37:49 +02:00
David Craven
7db0e71060
New api.
2018-03-27 20:17:44 +02:00