diff --git a/asm.S b/asm.S
index b10ff8e..041a4b5 100644
--- a/asm.S
+++ b/asm.S
@@ -44,7 +44,7 @@ __clear_ ## name: \
 
 // VexRiscv custom registers
 RW(0xBC0, vmim)     // Machine IRQ Mask
-RW(0xFC0, vmip)     // Machine IRQ Pending
+RO(0xFC0, vmip)     // Machine IRQ Pending
 RW(0x9C0, vsim)     // Supervisor IRQ Mask
-RW(0xDC0, vsip)     // Supervisor IRQ Pending
-RW(0xCC0, vdci)     // DCache Info
+RO(0xDC0, vsip)     // Supervisor IRQ Pending
+RO(0xCC0, vdci)     // DCache Info
diff --git a/src/register/vdci.rs b/src/register/vdci.rs
index 4c2c839..df2338a 100644
--- a/src/register/vdci.rs
+++ b/src/register/vdci.rs
@@ -1,4 +1,3 @@
 //! DCache Information register
 
 read_csr_as_usize!(0xCC0, __read_vdci);
-write_csr_as_usize!(0xCC0, __write_vdci);
diff --git a/src/register/vmip.rs b/src/register/vmip.rs
index 958e768..ce8e6cd 100644
--- a/src/register/vmip.rs
+++ b/src/register/vmip.rs
@@ -1,4 +1,3 @@
 //! Machine IRQ Pending register
 
 read_csr_as_usize!(0xFC0, __read_vmip);
-write_csr_as_usize!(0xFC0, __write_vmip);
diff --git a/src/register/vsip.rs b/src/register/vsip.rs
index 0c7b32c..76dfa54 100644
--- a/src/register/vsip.rs
+++ b/src/register/vsip.rs
@@ -1,4 +1,3 @@
 //! Supervisor IRQ Pending register
 
 read_csr_as_usize!(0xDC0, __read_vsip);
-write_csr_as_usize!(0xDC0, __write_vsip);