Merge #16

16: Build on stable r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

.gitignore

@@ -1,2 +1,5 @@
 Cargo.lock
 target/
+bin/*.after
+bin/*.before
+bin/*.o

.travis.yml

@@ -24,10 +24,19 @@ matrix:
       rust: nightly
       if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
 
+    - env: TARGET=x86_64-unknown-linux-gnu
+      rust: stable
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
+    - env: TARGET=riscv32imac-unknown-none-elf
+      rust: stable
+      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
+
 before_install: set -e
 
 install:
   - bash ci/install.sh
+  - export PATH="$PATH:$PWD/gcc/bin"
 
 script:
   - bash ci/script.sh

Cargo.toml

@@ -13,4 +13,5 @@ bare-metal = "0.2.0"
 bit_field = "0.9.0"
 
 [features]
+const-fn = ["bare-metal/const-fn"]
 inline-asm = []

asm.S

@@ -0,0 +1,55 @@
+#include "asm.h"
+
+.section .text.__ebreak
+.global __ebreak
+__ebreak:
+    ebreak
+    ret
+
+.section .text.__wfi
+.global __wfi
+__wfi:
+    wfi
+    ret
+
+.section .text.__sfence_vma_all
+.global __sfence_vma_all
+__sfence_vma_all:
+    sfence.vma
+    ret
+
+.section .text.__sfence_vma
+.global __sfence_vma
+__sfence_vma:
+    sfence.vma a0, a1
+    ret
+
+
+// M-mode registers
+REG_READ(mcause, 0x342)
+REG_READ(mcycle, 0xB00)
+REG_READ(mepc, 0x341)
+REG_READ(mie, 0x304)
+REG_SET_CLEAR(mie, 0x304)
+REG_READ(minstret, 0xB02)
+REG_READ(mip, 0x344)
+REG_READ(misa, 0x301)
+REG_READ(mstatus, 0x300)
+REG_SET_CLEAR(mstatus, 0x300)
+REG_READ_WRITE(mtvec, 0x305)
+REG_READ(mvendorid, 0xF11)
+
+// S-mode registers
+REG_READ_WRITE(satp, 0x180)
+REG_READ(scause, 0x142)
+REG_READ_WRITE(sepc, 0x141)
+REG_READ(sie, 0x104)
+REG_SET_CLEAR(sie, 0x104)
+REG_READ(sip, 0x144)
+REG_READ_WRITE(sscratch, 0x140)
+REG_READ(sstatus, 0x100)
+REG_SET_CLEAR(sstatus, 0x100)
+REG_READ(stval, 0x143)
+REG_READ_WRITE(stvec, 0x105)
+
+REG_READ(time, 0xC01)

asm.h

@@ -0,0 +1,37 @@
+#ifndef __ASM_H
+#define __ASM_H
+
+#define REG_READ(name, offset) \
+.section .text.__read_ ## name; \
+.global __read_ ## name; \
+__read_ ## name: \
+    csrrs a0, offset, x0; \
+    ret
+
+#define REG_WRITE(name, offset) \
+.section .text.__write_ ## name; \
+.global __write_ ## name; \
+__write_ ## name: \
+    csrrw x0, offset, a0; \
+    ret
+
+#define REG_SET(name, offset) \
+.section .text.__set_ ## name; \
+.global __set_ ## name; \
+__set_ ## name: \
+    csrrs x0, offset, a0; \
+    ret
+
+#define REG_CLEAR(name, offset) \
+.section .text.__clear_ ## name; \
+.global __clear_ ## name; \
+__clear_ ## name: \
+    csrrc x0, offset, a0; \
+    ret
+
+
+#define REG_READ_WRITE(name, offset) REG_READ(name, offset); REG_WRITE(name, offset)
+#define REG_SET_CLEAR(name, offset) REG_SET(name, offset); REG_CLEAR(name, offset)
+
+#endif /* __ASM_H */
+

asm32.S

@@ -0,0 +1,5 @@
+#include "asm.h"
+
+REG_READ(mcycleh, 0xB80)
+REG_READ(minstreth, 0xB82)
+REG_READ(timeh, 0xC81)

assemble.sh

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -euxo pipefail
+
+crate=riscv
+
+# remove existing blobs because otherwise this will append object files to the old blobs
+rm -f bin/*.a
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm32.S -o bin/$crate-32.o
+ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o bin/$crate-32.o
+cp bin/riscv32imac-unknown-none-elf.a bin/riscv32imc-unknown-none-elf.a
+
+rm bin/$crate.o
+rm bin/$crate-32.o

build.rs

@@ -0,0 +1,26 @@
+use std::path::PathBuf;
+use std::{env, fs};
+
+fn main() {
+    let target = env::var("TARGET").unwrap();
+    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
+    let name = env::var("CARGO_PKG_NAME").unwrap();
+
+    if target.starts_with("riscv") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() {
+        fs::copy(
+            format!("bin/{}.a", target),
+            out_dir.join(format!("lib{}.a", name)),
+        ).unwrap();
+
+        println!("cargo:rustc-link-lib=static={}", name);
+        println!("cargo:rustc-link-search={}", out_dir.display());
+    }
+
+    if target.starts_with("riscv32") {
+        println!("cargo:rustc-cfg=riscv");
+        println!("cargo:rustc-cfg=riscv32");
+    } else if target.starts_with("riscv64") {
+        println!("cargo:rustc-cfg=riscv");
+        println!("cargo:rustc-cfg=riscv64");
+    }
+}

check-blobs.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+
+# Checks that the blobs are up to date with the committed assembly files
+
+set -euxo pipefail
+
+for lib in $(ls bin/*.a); do
+    filename=$(basename $lib)
+    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.before
+done
+
+./assemble.sh
+
+for lib in $(ls bin/*.a); do
+    filename=$(basename $lib)
+    riscv64-unknown-elf-objdump -Cd $lib > bin/${filename%.a}.after
+done
+
+for cksum in $(ls bin/*.after); do
+    diff -u $cksum ${cksum%.after}.before
+done

ci/install.sh

@@ -4,6 +4,9 @@ main() {
     if [ $TARGET != x86_64-unknown-linux-gnu ]; then
         rustup target add $TARGET
     fi
+
+    mkdir gcc
+    curl -L https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2018.12.0-x86_64-linux-ubuntu14.tar.gz | tar --strip-components=1 -C gcc -xz
 }
 
 main

ci/script.sh

@@ -4,7 +4,11 @@ main() {
     cargo check --target $TARGET
 
     if [ $TRAVIS_RUST_VERSION = nightly ]; then
-        cargo check --target $TARGET --features inline-asm
+        cargo check --target $TARGET --features 'const-fn inline-asm'
+    fi
+
+    if [ $TARGET = x86_64-unknown-linux-gnu ]; then
+        ./check-blobs.sh
     fi
 }
 

src/asm.rs

@@ -1,13 +1,23 @@
 //! Assembly instructions
 
 macro_rules! instruction {
-    ($fnname:ident, $asm:expr) => (
+    ($fnname:ident, $asm:expr, $asm_fn:ident) => (
         #[inline]
         pub unsafe fn $fnname() {
             match () {
-                #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+                #[cfg(all(riscv, feature = "inline-asm"))]
                 () => asm!($asm :::: "volatile"),
-                #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+
+                #[cfg(all(riscv, not(feature = "inline-asm")))]
+                () => {
+                    extern "C" {
+                        fn $asm_fn();
+                    }
+
+                    $asm_fn();
+                }
+
+                #[cfg(not(riscv))]
                 () => unimplemented!(),
             }
         }
@@ -16,17 +26,28 @@ macro_rules! instruction {
 
 
 /// Priviledged ISA Instructions
-instruction!(ebreak, "ebreak");
+instruction!(ebreak, "ebreak", __ebreak);
-instruction!(wfi, "wfi");
+instruction!(wfi, "wfi", __wfi);
-instruction!(sfence_vma_all, "sfence.vma");
+instruction!(sfence_vma_all, "sfence.vma", __sfence_vma_all);
 
 
 #[inline]
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[allow(unused_variables)]
 pub unsafe fn sfence_vma(asid: usize, addr: usize) {
-    asm!("sfence.vma $0, $1" :: "r"(asid), "r"(addr) :: "volatile");
+    match () {
+        #[cfg(all(riscv, feature = "inline-asm"))]
+        () => asm!("sfence.vma $0, $1" :: "r"(asid), "r"(addr) :: "volatile"),
+
+        #[cfg(all(riscv, not(feature = "inline-asm")))]
+        () => {
+            extern "C" {
+                fn __sfence_vma(asid: usize, addr: usize);
             }
 
-#[inline]
+            __sfence_vma(asid, addr);
-#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        }
-pub fn sfence_vma(_asid: usize, _addr: usize) {}
+
+        #[cfg(not(riscv))]
+        () => unimplemented!(),
+    }
+}

src/interrupt.rs

@@ -8,9 +8,9 @@ use register::mstatus;
 #[inline]
 pub unsafe fn disable() {
     match () {
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        #[cfg(riscv)]
         () => mstatus::clear_mie(),
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        #[cfg(not(riscv))]
         () => unimplemented!(),
     }
 }
@@ -23,9 +23,9 @@ pub unsafe fn disable() {
 #[inline]
 pub unsafe fn enable() {
     match () {
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        #[cfg(riscv)]
         () => mstatus::set_mie(),
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        #[cfg(not(riscv))]
         () => unimplemented!(),
     }
 }

src/lib.rs

@@ -8,8 +8,7 @@
 
 #![no_std]
 #![deny(warnings)]
-#![feature(asm)]
+#![cfg_attr(feature = "inline-asm", feature(asm))]
-#![feature(const_fn)]
 
 extern crate bare_metal;
 extern crate bit_field;

src/register/macros.rs

@@ -1,44 +1,64 @@
 macro_rules! read_csr {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Reads the CSR
         #[inline]
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
         unsafe fn _read() -> usize {
+            match () {
+                #[cfg(all(riscv, feature = "inline-asm"))]
+                () => {
                     let r: usize;
                     asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile");
                     r
                 }
 
-        #[inline]
+                #[cfg(all(riscv, not(feature = "inline-asm")))]
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+                () => {
-        unsafe fn _read() -> usize {
+                    extern "C" {
-            unimplemented!()
+                        fn $asm_fn() -> usize;
+                    }
+
+                    $asm_fn()
+                }
+
+                #[cfg(not(riscv))]
+                () => unimplemented!(),
+            }
         }
     };
 }
 
 macro_rules! read_csr_rv32 {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Reads the CSR
         #[inline]
-        #[cfg(target_arch = "riscv32")]
         unsafe fn _read() -> usize {
+            match () {
+                #[cfg(all(riscv32, feature = "inline-asm"))]
+                () => {
                     let r: usize;
                     asm!("csrrs $0, $1, x0" : "=r"(r) : "i"($csr_number) :: "volatile");
                     r
                 }
 
-        #[inline]
+                #[cfg(all(riscv32, not(feature = "inline-asm")))]
-        #[cfg(not(target_arch = "riscv32"))]
+                () => {
-        unsafe fn _read() -> usize {
+                    extern "C" {
-            unimplemented!()
+                        fn $asm_fn() -> usize;
+                    }
+
+                    $asm_fn()
+                }
+
+                #[cfg(not(riscv32))]
+                () => unimplemented!(),
+            }
         }
     };
 }
 
 macro_rules! read_csr_as {
-    ($register:ident, $csr_number:expr) => {
+    ($register:ident, $csr_number:expr, $asm_fn: ident) => {
-        read_csr!($csr_number);
+        read_csr!($csr_number, $asm_fn);
 
         /// Reads the CSR
         #[inline]
@@ -49,8 +69,8 @@ macro_rules! read_csr_as {
 }
 
 macro_rules! read_csr_as_usize {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
-        read_csr!($csr_number);
+        read_csr!($csr_number, $asm_fn);
 
         /// Reads the CSR
         #[inline]
@@ -61,8 +81,8 @@ macro_rules! read_csr_as_usize {
 }
 
 macro_rules! read_csr_as_usize_rv32 {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
-        read_csr_rv32!($csr_number);
+        read_csr_rv32!($csr_number, $asm_fn);
 
         /// Reads the CSR
         #[inline]
@@ -73,25 +93,34 @@ macro_rules! read_csr_as_usize_rv32 {
 }
 
 macro_rules! write_csr {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Writes the CSR
         #[inline]
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        #[allow(unused_variables)]
         unsafe fn _write(bits: usize) {
-            asm!("csrrw x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
+            match () {
+                #[cfg(all(riscv, feature = "inline-asm"))]
+                () => asm!("csrrw x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"),
+
+                #[cfg(all(riscv, not(feature = "inline-asm")))]
+                () => {
+                    extern "C" {
+                        fn $asm_fn(bits: usize);
                     }
 
-        #[inline]
+                    $asm_fn(bits);
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+                }
-        unsafe fn _write(_bits: usize) {
+
-            unimplemented!()
+                #[cfg(not(riscv))]
+                () => unimplemented!(),
+            }
         }
     };
 }
 
 macro_rules! write_csr_as_usize {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
-        write_csr!($csr_number);
+        write_csr!($csr_number, $asm_fn);
 
         /// Writes the CSR
         #[inline]
@@ -102,35 +131,53 @@ macro_rules! write_csr_as_usize {
 }
 
 macro_rules! set {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Set the CSR
         #[inline]
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        #[allow(unused_variables)]
         unsafe fn _set(bits: usize) {
-            asm!("csrrs x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
+            match () {
+                #[cfg(all(riscv, feature = "inline-asm"))]
+                () => asm!("csrrs x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"),
+
+                #[cfg(all(riscv, not(feature = "inline-asm")))]
+                () => {
+                    extern "C" {
+                        fn $asm_fn(bits: usize);
                     }
 
-        #[inline]
+                    $asm_fn(bits);
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+                }
-        unsafe fn _set(_bits: usize) {
+
-            unimplemented!()
+                #[cfg(not(riscv))]
+                () => unimplemented!(),
+            }
         }
     };
 }
 
 macro_rules! clear {
-    ($csr_number:expr) => {
+    ($csr_number:expr, $asm_fn: ident) => {
         /// Clear the CSR
         #[inline]
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        #[allow(unused_variables)]
         unsafe fn _clear(bits: usize) {
-            asm!("csrrc x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile");
+            match () {
+                #[cfg(all(riscv, feature = "inline-asm"))]
+                () => asm!("csrrc x0, $1, $0" :: "r"(bits), "i"($csr_number) :: "volatile"),
+
+                #[cfg(all(riscv, not(feature = "inline-asm")))]
+                () => {
+                    extern "C" {
+                        fn $asm_fn(bits: usize);
                     }
 
-        #[inline]
+                    $asm_fn(bits);
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+                }
-        unsafe fn _clear(_bits: usize) {
+
-            unimplemented!()
+                #[cfg(not(riscv))]
+                () => unimplemented!(),
+            }
         }
     };
 }

src/register/mcause.rs

@@ -136,4 +136,4 @@ impl Mcause {
     }
 }
 
-read_csr_as!(Mcause, 0x342);
+read_csr_as!(Mcause, 0x342, __read_mcause);

src/register/mcycle.rs

@@ -1,3 +1,3 @@
 //! mcycle register
 
-read_csr_as_usize!(0xB00);
+read_csr_as_usize!(0xB00, __read_mcycle);

src/register/mcycleh.rs

@@ -1,3 +1,3 @@
 //! mcycleh register
 
-read_csr_as_usize_rv32!(0xB80);
+read_csr_as_usize_rv32!(0xB80, __read_mcycleh);

src/register/mepc.rs

@@ -1,3 +1,3 @@
 //! mepc register
 
-read_csr_as_usize!(0x341);
+read_csr_as_usize!(0x341, __read_mepc);

src/register/mie.rs

@@ -68,9 +68,9 @@ impl Mie {
     }
 }
 
-read_csr_as!(Mie, 0x304);
+read_csr_as!(Mie, 0x304, __read_mie);
-set!(0x304);
+set!(0x304, __set_mie);
-clear!(0x304);
+clear!(0x304, __clear_mie);
 
 /// User Software Interrupt Enable
 set_clear_csr!(set_usoft, clear_usoft, 1 << 0);

src/register/minstret.rs

@@ -1,3 +1,3 @@
 //! minstret register
 
-read_csr_as_usize!(0xB02);
+read_csr_as_usize!(0xB02, __read_minstret);

src/register/minstreth.rs

@@ -1,3 +1,3 @@
 //! minstreth register
 
-read_csr_as_usize_rv32!(0xB82);
+read_csr_as_usize_rv32!(0xB82, __read_minstreth);

src/register/mip.rs

@@ -68,4 +68,4 @@ impl Mip {
     }
 }
 
-read_csr_as!(Mip, 0x344);
+read_csr_as!(Mip, 0x344, __read_mip);

src/register/misa.rs

@@ -47,7 +47,7 @@ impl Misa {
     }
 }
 
-read_csr!(0x301);
+read_csr!(0x301, __read_misa);
 
 /// Reads the CSR
 #[inline]

src/register/mstatus.rs

@@ -79,9 +79,9 @@ impl Mstatus {
 }
 
 
-read_csr_as!(Mstatus, 0x300);
+read_csr_as!(Mstatus, 0x300, __read_mstatus);
-set!(0x300);
+set!(0x300, __set_mstatus);
-clear!(0x300);
+clear!(0x300, __clear_mstatus);
 
 /// User Interrupt Enable
 set_clear_csr!(set_uie, clear_uie, 1 << 0);

src/register/mtvec.rs

@@ -34,9 +34,9 @@ impl Mtvec {
     }
 }
 
-read_csr_as!(Mtvec, 0x305);
+read_csr_as!(Mtvec, 0x305, __read_mtvec);
 
-write_csr!(0x305);
+write_csr!(0x305, __write_mtvec);
 
 /// Writes the CSR
 #[inline]

src/register/mvendorid.rs

@@ -20,7 +20,7 @@ impl Mvendorid {
     }
 }
 
-read_csr!(0xF11);
+read_csr!(0xF11, __read_mvendorid);
 
 /// Reads the CSR
 #[inline]

src/register/satp.rs

@@ -1,6 +1,6 @@
 //! satp register
 
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[cfg(riscv)]
 use bit_field::BitField;
 
 /// satp register
@@ -18,7 +18,7 @@ impl Satp {
 
     /// Current address-translation scheme
     #[inline]
-    #[cfg(target_arch = "riscv32")]
+    #[cfg(riscv32)]
     pub fn mode(&self) -> Mode {
         match self.bits.get_bit(31) {
             false => Mode::Bare,
@@ -28,7 +28,7 @@ impl Satp {
 
     /// Current address-translation scheme
     #[inline]
-    #[cfg(target_arch = "riscv64")]
+    #[cfg(riscv64)]
     pub fn mode(&self) -> Mode {
         match self.bits.get_bits(60..64) {
             0 => Mode::Bare,
@@ -42,40 +42,40 @@ impl Satp {
 
     /// Address space identifier
     #[inline]
-    #[cfg(target_arch = "riscv32")]
+    #[cfg(riscv32)]
     pub fn asid(&self) -> usize {
         self.bits.get_bits(22..31)
     }
 
     /// Address space identifier
     #[inline]
-    #[cfg(target_arch = "riscv64")]
+    #[cfg(riscv64)]
     pub fn asid(&self) -> usize {
         self.bits.get_bits(44..60)
     }
 
     /// Physical page number
     #[inline]
-    #[cfg(target_arch = "riscv32")]
+    #[cfg(riscv32)]
     pub fn ppn(&self) -> usize {
         self.bits.get_bits(0..22)
     }
 
     /// Physical page number
     #[inline]
-    #[cfg(target_arch = "riscv64")]
+    #[cfg(riscv64)]
     pub fn ppn(&self) -> usize {
         self.bits.get_bits(0..44)
     }
 }
 
-#[cfg(target_arch = "riscv32")]
+#[cfg(riscv32)]
 pub enum Mode {
     Bare = 0,
     Sv32 = 1,
 }
 
-#[cfg(target_arch = "riscv64")]
+#[cfg(riscv64)]
 pub enum Mode {
     Bare = 0,
     Sv39 = 8,
@@ -84,11 +84,11 @@ pub enum Mode {
     Sv64 = 11,
 }
 
-read_csr_as!(Satp, 0x180);
+read_csr_as!(Satp, 0x180, __read_satp);
-write_csr!(0x180);
+write_csr!(0x180, __write_satp);
 
 #[inline]
-#[cfg(target_arch = "riscv32")]
+#[cfg(riscv32)]
 pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
     let mut bits = 0usize;
     bits.set_bits(31..32, mode as usize);
@@ -98,7 +98,7 @@ pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
 }
 
 #[inline]
-#[cfg(target_arch = "riscv64")]
+#[cfg(riscv64)]
 pub unsafe fn set(mode: Mode, asid: usize, ppn: usize) {
     let mut bits = 0usize;
     bits.set_bits(60..64, mode as usize);

src/register/scause.rs

@@ -115,4 +115,4 @@ impl Scause {
     }
 }
 
-read_csr_as!(Scause, 0x142);
+read_csr_as!(Scause, 0x142, __read_scause);

src/register/sepc.rs

@@ -1,4 +1,4 @@
 //! sepc register
 
-read_csr_as_usize!(0x141);
+read_csr_as_usize!(0x141, __read_sepc);
-write_csr_as_usize!(0x141);
+write_csr_as_usize!(0x141, __write_sepc);

src/register/sie.rs

@@ -52,9 +52,9 @@ impl Sie {
     }
 }
 
-read_csr_as!(Sie, 0x104);
+read_csr_as!(Sie, 0x104, __read_sie);
-set!(0x104);
+set!(0x104, __set_sie);
-clear!(0x104);
+clear!(0x104, __clear_sie);
 
 /// User Software Interrupt Enable
 set_clear_csr!(set_usoft, clear_usoft, 1 << 0);

src/register/sip.rs

@@ -52,4 +52,4 @@ impl Sip {
     }
 }
 
-read_csr_as!(Sip, 0x144);
+read_csr_as!(Sip, 0x144, __read_sip);

src/register/sscratch.rs

@@ -1,4 +1,4 @@
 //! sscratch register
 
-read_csr_as_usize!(0x140);
+read_csr_as_usize!(0x140, __read_sscratch);
-write_csr_as_usize!(0x140);
+write_csr_as_usize!(0x140, __write_sscratch);

src/register/sstatus.rs

@@ -104,9 +104,9 @@ impl Sstatus {
     }
 }
 
-read_csr_as!(Sstatus, 0x100);
+read_csr_as!(Sstatus, 0x100, __read_sstatus);
-set!(0x100);
+set!(0x100, __set_sstatus);
-clear!(0x100);
+clear!(0x100, __clear_sstatus);
 
 /// User Interrupt Enable
 set_clear_csr!(set_uie, clear_uie, 1 << 0);
@@ -123,14 +123,14 @@ set_clear_csr!(set_sum, clear_sum, 1 << 18);
 
 /// Supervisor Previous Privilege Mode
 #[inline]
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[cfg(riscv)]
 pub unsafe fn set_spp(spp: SPP) {
     _set((spp as usize) << 8);
 }
 
 /// The status of the floating-point unit
 #[inline]
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+#[cfg(riscv)]
 pub unsafe fn set_fs(fs: FS) {
     _set((fs as usize) << 13);
 }

src/register/stval.rs

@@ -1,3 +1,3 @@
 //! stval register
 
-read_csr_as_usize!(0x143);
+read_csr_as_usize!(0x143, __read_stval);

src/register/stvec.rs

@@ -34,8 +34,8 @@ impl Stvec {
     }
 }
 
-read_csr_as!(Stvec, 0x105);
+read_csr_as!(Stvec, 0x105, __read_stvec);
-write_csr!(0x105);
+write_csr!(0x105, __write_stvec);
 
 /// Writes the CSR
 #[inline]

src/register/time.rs

@@ -1,3 +1,3 @@
 //! time register
 
-read_csr_as_usize!(0xC01);
+read_csr_as_usize!(0xC01, __read_time);

src/register/timeh.rs

@@ -1,3 +1,3 @@
 //! timeh register
 
-read_csr_as_usize_rv32!(0xC81);
+read_csr_as_usize_rv32!(0xC81, __read_timeh);