From cd5200c5fa72f69078b3b838c356c25cc41e7ae6 Mon Sep 17 00:00:00 2001
From: David Craven <david@craven.ch>
Date: Thu, 29 Mar 2018 15:37:49 +0200
Subject: [PATCH] Fix mstatus register value.

---
 src/register/mstatus.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/register/mstatus.rs b/src/register/mstatus.rs
index b49bebb..0f1ed03 100644
--- a/src/register/mstatus.rs
+++ b/src/register/mstatus.rs
@@ -102,7 +102,7 @@ pub fn read() -> Mstatus {
 unsafe fn set(bits: usize) {
     match () {
         #[cfg(target_arch = "riscv")]
-        () => asm!("csrrs x0, 0x305, $0" :: "r"(bits) :: "volatile"),
+        () => asm!("csrrs x0, 0x300, $0" :: "r"(bits) :: "volatile"),
         #[cfg(not(target_arch = "riscv"))]
         () => unimplemented!(),
     }
@@ -114,7 +114,7 @@ unsafe fn set(bits: usize) {
 unsafe fn clear(bits: usize) {
     match () {
         #[cfg(target_arch = "riscv")]
-        () => asm!("csrrc x0, 0x305, $0" :: "r"(bits) :: "volatile"),
+        () => asm!("csrrc x0, 0x300, $0" :: "r"(bits) :: "volatile"),
         #[cfg(not(target_arch = "riscv"))]
         () => unimplemented!(),
     }