New api.
This commit is contained in:
David Craven
parent
179df42984
commit
7db0e71060
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@ -9,5 +9,4 @@ keywords = ["riscv", "register", "peripheral"]
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license = "ISC"
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[dependencies]
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bare-metal = "^0.1.1"
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volatile-register = "^0.2.0"
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bare-metal = "0.1.1"
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79
README.md
79
README.md
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@ -2,6 +2,85 @@
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> Low level access to RISCV processors
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## Implemented Peripherals
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- [ ] plic
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- [ ] clint
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## Implemented privileged ASM instructions
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- [x] ecall
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- [x] ebreak
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- [x] uret
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- [x] sret
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- [x] mret
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- [x] wfi
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- [ ] sfence.vma
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## Implemented CSR's
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### User mode
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- [ ] ustatus
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- [ ] uie
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- [ ] utvec
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- [ ] uscratch
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- [ ] uepc
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- [ ] ucause
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- [ ] utval
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- [ ] uip
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- [ ] fflags
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- [ ] frm
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- [ ] fcsr
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- [ ] cycle
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- [ ] time
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- [ ] instret
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- [ ] hpmcounter[3-31]
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- [ ] cycleh
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- [ ] timeh
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- [ ] instreth
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- [ ] hpmcounter[3-31]h
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### Supervisor mode
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- [ ] sstatus
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- [ ] sedeleg
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- [ ] sideleg
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- [ ] sie
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- [ ] stvec
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- [ ] scounteren
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- [ ] sscratch
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- [ ] sepc
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- [ ] scause
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- [ ] stval
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- [ ] sip
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- [ ] satp
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### Machine mode
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- [x] mvendorid
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- [ ] marchid
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- [ ] mimpid
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- [ ] mhartid
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- [x] mstatus
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- [x] misa
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- [ ] medeleg
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- [ ] mideleg
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- [x] mie
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- [x] mtvec
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- [ ] mcounteren
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- [ ] mscratch
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- [ ] mepc
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- [x] mcause
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- [ ] mtval
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- [x] mip
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- [ ] pmpcfg[0-3]
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- [ ] pmpaddr[0-15]
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- [x] mcycle
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- [x] minstret
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- [ ] mhpmcounter[3-31]
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- [x] mcycleh
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- [x] minstreth
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- [ ] mhpmcounter[3-31]h
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- [ ] mhpmevent[3-31]
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- [ ] tselect
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- [ ] tdata[1-3]
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# License
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Copyright 2017 David Craven
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10
src/asm.rs
10
src/asm.rs
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@ -17,16 +17,10 @@ macro_rules! instruction {
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}
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/// User Level ISA instructions
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instruction!(nop, "addi zero, zero, 0");
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/// Priviledged ISA Instructions
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instruction!(ecall, "ecall");
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instruction!(ebreak, "ebreak");
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instruction!(fence, "fence iorw, iorw");
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instruction!(fencei, "fence.i");
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/// Priviledged ISA Instructions
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instruction!(wfi, "wfi");
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instruction!(uret, "uret");
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instruction!(sret, "sret");
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instruction!(mret, "mret");
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instruction!(sfencevma, "sfence.vma");
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instruction!(wfi, "wfi");
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606
src/csr.rs
606
src/csr.rs
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@ -1,606 +0,0 @@
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//! Functions for accessing Control and Status Registers
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#[cfg(target_arch = "riscv")]
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macro_rules! csr_asm {
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($op:ident, $csr:expr, $value:expr) => (
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{
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let res: usize;
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unsafe {
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asm!(concat!(stringify!($op), " $0, ", stringify!($csr), ", $1")
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: "=r"(res)
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: "r"($value)
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:
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: "volatile");
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}
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res
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}
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)
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}
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#[cfg(not(target_arch = "riscv"))]
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macro_rules! csr_asm {
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($op:ident, $csr:expr, $value:expr) => {
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0
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}
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}
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macro_rules! r {
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($MOD:ident, $TYPE:ident, $CSR:expr) => (
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pub struct R {
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bits: u32,
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}
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impl super::$TYPE {
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#[inline]
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pub fn read(&self) -> R {
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R { bits: csr_asm!(csrrs, $CSR, 0) as u32 }
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}
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}
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impl R {
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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}
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)
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}
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macro_rules! w {
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($MOD:ident, $TYPE:ident, $CSR:expr) => (
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macro_rules! func {
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($fnname:ident, $csrop:ident) => (
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#[inline(always)]
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pub fn $fnname<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W { bits: 0 };
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f(&mut w);
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csr_asm!($csrop, $CSR, w.bits as usize);
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}
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)
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}
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pub struct W {
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bits: u32,
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}
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impl super::$TYPE {
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func!(write, csrrw);
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func!(set, csrrs);
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func!(clear, csrrc);
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}
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impl W {
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#[inline]
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pub fn bits(&mut self, value: u32) -> &mut W {
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self.bits = value;
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self
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}
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#[inline]
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pub fn set_bits(&mut self, value: u32) -> &mut W {
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self.bits |= value;
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self
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}
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#[inline]
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pub fn clear_bits(&mut self, value: u32) -> &mut W {
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self.bits &= !value;
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self
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}
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}
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)
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}
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macro_rules! rw {
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($MOD:ident, $TYPE:ident, $CSR:expr) => (
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r!($MOD, $TYPE, $CSR);
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w!($MOD, $TYPE, $CSR);
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)
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}
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macro_rules! csr {
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($MOD:ident, $TYPE:ident, $CSR:expr, $MACRO:ident) => (
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pub struct $TYPE {}
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#[allow(non_upper_case_globals)]
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pub const $MOD: $TYPE = $TYPE {};
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pub mod $MOD {
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$MACRO!($MOD, $TYPE, $CSR);
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}
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)
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}
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/// User Trap Setup
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csr!(ustatus, USTATUS, 0x000, rw);
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csr!(uie, UIE, 0x004, rw);
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csr!(utvec, UTVEC, 0x005, rw);
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/// User Trap Handling
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csr!(uscratch, USCRATCH, 0x040, rw);
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csr!(uepc, UEPC, 0x041, rw);
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csr!(ucause, UCAUSE, 0x042, rw);
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csr!(utval, UTVAL, 0x043, rw);
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csr!(uip, UIP, 0x044, r);
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/// User Floating-Point CSRs
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csr!(fflags, FFLAGS, 0x001, rw);
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csr!(frm, FRM, 0x002, rw);
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csr!(fcsr, FCSR, 0x003, rw);
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/// User Counter/Timers
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csr!(cycle, CYCLE, 0xC00, rw);
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csr!(time, TIME, 0xC01, rw);
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csr!(instret, INSTRET, 0xC02, rw);
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// TODO: hpmcounter3 - hpmcounter31
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csr!(cycleh, CYCLEH, 0xC80, rw);
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csr!(timeh, TIMEH, 0xC81, rw);
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csr!(instreth, INSTRETH, 0xC82, rw);
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// TODO: hpmcounter3h - hpmcounter31h
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/// Supervisor Trap Setup
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csr!(sstatus, SSTATUS, 0x100, rw);
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csr!(sedeleg, SEDELEG, 0x102, rw);
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csr!(sideleg, SIDELEG, 0x103, rw);
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csr!(sie, SIE, 0x104, rw);
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csr!(stvec, STVEC, 0x105, rw);
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csr!(scounteren, SCOUNTEREN, 0x106, rw);
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/// Supervisor Trap Handling
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csr!(sscratch, SSCRATCH, 0x140, rw);
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csr!(sepc, SEPC, 0x141, rw);
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csr!(scause, SCAUSE, 0x142, rw);
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csr!(stval, STVAL, 0x143, rw);
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csr!(sip, SIP, 0x144, r);
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/// Supervisor Protection and Translation
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csr!(satp, SATP, 0x180, rw);
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/// Machine Information Registers
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csr!(mvendorid, MVENDORID, 0xF11, r);
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csr!(marchid, MARCHID, 0xF12, r);
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csr!(mimpid, MIMPID, 0xF13, r);
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csr!(mhartid, MHARTID, 0xF14, r);
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/// Machine Trap Setup
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csr!(mstatus, MSTATUS, 0x300, rw);
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csr!(misa, MISA, 0x301, r);
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csr!(medeleg, MEDELEG, 0x302, rw);
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csr!(mideleg, MIDELEG, 0x303, rw);
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csr!(mie, MIE, 0x304, rw);
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csr!(mtvec, MTVEC, 0x305, rw);
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csr!(mcounteren, MCOUNTEREN, 0x306, rw);
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/// Machine Trap Handling
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csr!(mscratch, MSCRATCH, 0x340, rw);
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csr!(mepc, MEPC, 0x341, rw);
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csr!(mcause, MCAUSE, 0x342, r);
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csr!(mtval, MTVAL, 0x343, rw);
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csr!(mip, MIP, 0x344, r);
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/// Machine Protection and Translation
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csr!(pmpcfg0, PMPCFG0, 0x3A0, rw);
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csr!(pmpcfg1, PMPCFG1, 0x3A1, rw);
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csr!(pmpcfg2, PMPCFG2, 0x3A2, rw);
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csr!(pmpcfg3, PMPCFG3, 0x3A3, rw);
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// TODO pmpaddr0 - pmpaddr15
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/// Machine Counter/Timers
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csr!(mcycle, MCYCLE, 0xB00, rw);
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csr!(minstret, MINSTRET, 0xB02, rw);
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// TODO mhpmcounter3 .. mhpmcounter31
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csr!(mcycleh, MCYCLEH, 0xB80, rw);
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csr!(minstreth, MINSTRETH, 0xB82, rw);
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// TODO mhpmcounter3h .. mhpmcounter31h
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/// Machine Counter Setup
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// TODO mhpmevent3 .. mhpmevent31
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/// Debug/Trace Registers (shared with Debug Mode)
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csr!(tselect, TSELECT, 0x7A0, rw);
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csr!(tdata1, TDATA1, 0x7A1, rw);
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csr!(tdata2, TDATA2, 0x7A2, rw);
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csr!(tdata3, TDATA3, 0x7A3, rw);
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/// Debug Mode Registers
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csr!(dcsr, DCSR, 0x7B0, rw);
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csr!(dpc, DPC, 0x7B1, rw);
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csr!(dscratch, DSCRATCH, 0x7B2, rw);
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/// Machine Cause CSR (mcause) is ReadOnly.
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/// Trap Cause
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#[derive(Copy, Clone, Debug)]
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pub enum Trap {
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Interrupt(Interrupt),
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Exception(Exception),
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}
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/// Interrupt
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#[derive(Copy, Clone, Debug)]
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pub enum Interrupt {
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UserSoft,
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SupervisorSoft,
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MachineSoft,
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UserTimer,
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SupervisorTimer,
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MachineTimer,
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UserExternal,
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SupervisorExternal,
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MachineExternal,
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}
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impl Interrupt {
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pub fn from(nr: u32) -> Self {
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match nr {
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0 => Interrupt::UserSoft,
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1 => Interrupt::SupervisorSoft,
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3 => Interrupt::MachineSoft,
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4 => Interrupt::UserTimer,
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5 => Interrupt::SupervisorTimer,
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7 => Interrupt::MachineTimer,
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8 => Interrupt::UserExternal,
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9 => Interrupt::SupervisorExternal,
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11 => Interrupt::MachineExternal,
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_ => unreachable!()
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}
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}
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}
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/// Exception
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#[derive(Copy, Clone, Debug)]
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pub enum Exception {
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InstructionMisaligned,
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InstructionFault,
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IllegalInstruction,
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Breakpoint,
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LoadMisaligned,
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LoadFault,
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StoreMisaligned,
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StoreFault,
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UserEnvCall,
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SupervisorEnvCall,
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MachineEnvCall,
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InstructionPageFault,
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LoadPageFault,
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StorePageFault,
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}
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impl Exception {
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pub fn from(nr: u32) -> Self {
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match nr {
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0 => Exception::InstructionMisaligned,
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1 => Exception::InstructionFault,
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2 => Exception::IllegalInstruction,
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3 => Exception::Breakpoint,
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4 => Exception::LoadMisaligned,
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5 => Exception::LoadFault,
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6 => Exception::StoreMisaligned,
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7 => Exception::StoreFault,
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8 => Exception::UserEnvCall,
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9 => Exception::SupervisorEnvCall,
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11 => Exception::MachineEnvCall,
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12 => Exception::InstructionPageFault,
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13 => Exception::LoadPageFault,
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15 => Exception::StorePageFault,
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_ => unreachable!()
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}
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}
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}
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impl mcause::R {
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#[inline]
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/// Trap Cause
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pub fn cause(&self) -> Trap {
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let bits = self.bits();
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let code = bits & !(1 << 31);
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match bits & (1 << 31) == 1 << 31 {
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true => Trap::Interrupt(Interrupt::from(code)),
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false => Trap::Exception(Exception::from(code)),
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}
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}
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#[inline]
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/// Is trap cause an interrupt.
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pub fn is_interrupt(&self) -> bool {
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match self.cause() {
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Trap::Interrupt(_) => true,
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_ => false,
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}
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}
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#[inline]
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/// Is trap cause an exception.
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pub fn is_exception(&self) -> bool {
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match self.cause() {
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Trap::Exception(_) => true,
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_ => false,
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}
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}
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}
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/// Machine Status CSR is ReadWrite
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// TODO: Virtualization, Memory Privilege and Extension Context Fields
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/// Machine Previous Privilege Mode
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pub enum MPP {
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Machine = 3,
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Supervisor = 1,
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User = 0,
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}
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/// Supervisor Previous Privilege Mode
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pub enum SPP {
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Supervisor = 1,
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User = 0,
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}
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impl mstatus::R {
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#[inline]
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/// User Interrupt Enable
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pub fn uie(&self) -> bool {
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self.bits() & (1 << 0) == 1 << 0
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}
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#[inline]
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/// Supervisor Interrupt Enable
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pub fn sie(&self) -> bool {
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self.bits() & (1 << 1) == 1 << 1
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}
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#[inline]
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/// Machine Interrupt Enable
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pub fn mie(&self) -> bool {
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self.bits() & (1 << 3) == 1 << 3
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}
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#[inline]
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/// User Previous Interrupt Enable
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pub fn upie(&self) -> bool {
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self.bits() & (1 << 4) == 1 << 4
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}
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#[inline]
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/// Supervisor Previous Interrupt Enable
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pub fn spie(&self) -> bool {
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self.bits() & (1 << 5) == 1 << 5
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}
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#[inline]
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/// User Previous Interrupt Enable
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pub fn mpie(&self) -> bool {
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self.bits() & (1 << 7) == 1 << 7
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}
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#[inline]
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/// Supervisor Previous Privilege Mode
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pub fn spp(&self) -> SPP {
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match self.bits() & (1 << 8) == (1 << 8) {
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true => SPP::Supervisor,
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false => SPP::User,
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}
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}
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#[inline]
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/// Machine Previous Privilege Mode
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pub fn mpp(&self) -> MPP {
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match (self.bits() & (0b11 << 11)) >> 11 {
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0b00 => MPP::User,
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0b01 => MPP::Supervisor,
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0b11 => MPP::Machine,
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_ => unreachable!(),
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}
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}
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}
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impl mstatus::W {
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#[inline]
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/// User Interrupt Enable
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pub fn uie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 0)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Interrupt Enable
|
||||
pub fn sie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 1)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Interrupt Enable
|
||||
pub fn mie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 3)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn upie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 4)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn spie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 5)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn mpie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 7)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Previous Privilege Mode
|
||||
pub fn spp(&mut self, value: SPP) -> &mut mstatus::W {
|
||||
self.set_bits((value as u32) << 8)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Previous Privilege Mode
|
||||
pub fn mpp(&mut self, value: MPP) -> &mut mstatus::W {
|
||||
self.set_bits((value as u32) << 11)
|
||||
}
|
||||
}
|
||||
|
||||
/// Machine Interrupt Enable CSR (mie) is ReadWrite.
|
||||
impl mie::R {
|
||||
#[inline]
|
||||
/// User Software Interrupt Enable
|
||||
pub fn usoft(&self) -> bool {
|
||||
self.bits() & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Software Interrupt Enable
|
||||
pub fn ssoft(&self) -> bool {
|
||||
self.bits() & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Software Interrupt Enable
|
||||
pub fn msoft(&self) -> bool {
|
||||
self.bits() & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User Timer Interrupt Enable
|
||||
pub fn utimer(&self) -> bool {
|
||||
self.bits() & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
pub fn stimer(&self) -> bool {
|
||||
self.bits() & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Timer Interrupt Enable
|
||||
pub fn mtimer(&self) -> bool {
|
||||
self.bits() & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User External Interrupt Enable
|
||||
pub fn uext(&self) -> bool {
|
||||
self.bits() & (1 << 8) == 1 << 8
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor External Interrupt Enable
|
||||
pub fn sext(&self) -> bool {
|
||||
self.bits() & (1 << 9) == 1 << 9
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine External Interrupt Enable
|
||||
pub fn mext(&self) -> bool {
|
||||
self.bits() & (1 << 11) == 1 << 11
|
||||
}
|
||||
}
|
||||
|
||||
impl mie::W {
|
||||
#[inline]
|
||||
/// User Software Interrupt Enable
|
||||
pub fn usoft(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 0)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Software Interrupt Enable
|
||||
pub fn ssoft(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 1)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Software Interrupt Enable
|
||||
pub fn msoft(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 3)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User Timer Interrupt Enable
|
||||
pub fn utimer(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 4)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
pub fn stimer(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 5)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Timer Interrupt Enable
|
||||
pub fn mtimer(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 7)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User External Interrupt Enable
|
||||
pub fn uext(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 8)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor External Interrupt Enable
|
||||
pub fn sext(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 9)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine External Interrupt Enable
|
||||
pub fn mext(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 11)
|
||||
}
|
||||
}
|
||||
|
||||
/// Machine Interrupt Pending CSR (mip) is ReadOnly.
|
||||
impl mip::R {
|
||||
#[inline]
|
||||
/// User Software Interrupt Enable
|
||||
pub fn usoft(&self) -> bool {
|
||||
self.bits() & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Software Interrupt Enable
|
||||
pub fn ssoft(&self) -> bool {
|
||||
self.bits() & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Software Interrupt Enable
|
||||
pub fn msoft(&self) -> bool {
|
||||
self.bits() & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User Timer Interrupt Enable
|
||||
pub fn utimer(&self) -> bool {
|
||||
self.bits() & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
pub fn stimer(&self) -> bool {
|
||||
self.bits() & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine Timer Interrupt Enable
|
||||
pub fn mtimer(&self) -> bool {
|
||||
self.bits() & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// User External Interrupt Enable
|
||||
pub fn uext(&self) -> bool {
|
||||
self.bits() & (1 << 8) == 1 << 8
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Supervisor External Interrupt Enable
|
||||
pub fn sext(&self) -> bool {
|
||||
self.bits() & (1 << 9) == 1 << 9
|
||||
}
|
||||
|
||||
#[inline]
|
||||
/// Machine External Interrupt Enable
|
||||
pub fn mext(&self) -> bool {
|
||||
self.bits() & (1 << 11) == 1 << 11
|
||||
}
|
||||
}
|
||||
|
|
@ -2,13 +2,14 @@
|
|||
|
||||
// NOTE: Adapted from cortex-m/src/interrupt.rs
|
||||
pub use bare_metal::{CriticalSection, Mutex, Nr};
|
||||
use register::mstatus;
|
||||
|
||||
/// Disables all interrupts
|
||||
#[inline]
|
||||
pub fn disable() {
|
||||
pub unsafe fn disable() {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => ::csr::mstatus.clear(|w| w.mie()),
|
||||
() => mstatus::clear_mie(),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => {}
|
||||
}
|
||||
|
|
@ -23,7 +24,7 @@ pub fn disable() {
|
|||
pub unsafe fn enable() {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => ::csr::mstatus.set(|w| w.mie()),
|
||||
() => mstatus::set_mie(),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => {}
|
||||
}
|
||||
|
|
@ -36,17 +37,17 @@ pub fn free<F, R>(f: F) -> R
|
|||
where
|
||||
F: FnOnce(&CriticalSection) -> R,
|
||||
{
|
||||
let mstatus = ::csr::mstatus.read();
|
||||
let mstatus = mstatus::read();
|
||||
|
||||
// disable interrupts
|
||||
disable();
|
||||
unsafe { disable(); }
|
||||
|
||||
let r = f(unsafe { &CriticalSection::new() });
|
||||
|
||||
// If the interrupts were active before our `disable` call, then re-enable
|
||||
// them. Otherwise, keep them disabled
|
||||
if mstatus.mie() {
|
||||
unsafe { enable() }
|
||||
unsafe { enable(); }
|
||||
}
|
||||
|
||||
r
|
||||
|
|
|
|||
|
|
@ -14,5 +14,5 @@
|
|||
extern crate bare_metal;
|
||||
|
||||
pub mod asm;
|
||||
pub mod csr;
|
||||
pub mod interrupt;
|
||||
pub mod register;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,154 @@
|
|||
//! mcause register
|
||||
|
||||
/// mcause register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Mcause {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
/// Trap Cause
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub enum Trap {
|
||||
Interrupt(Interrupt),
|
||||
Exception(Exception),
|
||||
}
|
||||
|
||||
/// Interrupt
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub enum Interrupt {
|
||||
UserSoft,
|
||||
SupervisorSoft,
|
||||
MachineSoft,
|
||||
UserTimer,
|
||||
SupervisorTimer,
|
||||
MachineTimer,
|
||||
UserExternal,
|
||||
SupervisorExternal,
|
||||
MachineExternal,
|
||||
Unknown,
|
||||
}
|
||||
|
||||
/// Exception
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub enum Exception {
|
||||
InstructionMisaligned,
|
||||
InstructionFault,
|
||||
IllegalInstruction,
|
||||
Breakpoint,
|
||||
LoadMisaligned,
|
||||
LoadFault,
|
||||
StoreMisaligned,
|
||||
StoreFault,
|
||||
UserEnvCall,
|
||||
SupervisorEnvCall,
|
||||
MachineEnvCall,
|
||||
InstructionPageFault,
|
||||
LoadPageFault,
|
||||
StorePageFault,
|
||||
Unknown,
|
||||
}
|
||||
|
||||
impl Interrupt {
|
||||
pub fn from(nr: usize) -> Self {
|
||||
match nr {
|
||||
0 => Interrupt::UserSoft,
|
||||
1 => Interrupt::SupervisorSoft,
|
||||
3 => Interrupt::MachineSoft,
|
||||
4 => Interrupt::UserTimer,
|
||||
5 => Interrupt::SupervisorTimer,
|
||||
7 => Interrupt::MachineTimer,
|
||||
8 => Interrupt::UserExternal,
|
||||
9 => Interrupt::SupervisorExternal,
|
||||
11 => Interrupt::MachineExternal,
|
||||
_ => Interrupt::Unknown,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
impl Exception {
|
||||
pub fn from(nr: usize) -> Self {
|
||||
match nr {
|
||||
0 => Exception::InstructionMisaligned,
|
||||
1 => Exception::InstructionFault,
|
||||
2 => Exception::IllegalInstruction,
|
||||
3 => Exception::Breakpoint,
|
||||
4 => Exception::LoadMisaligned,
|
||||
5 => Exception::LoadFault,
|
||||
6 => Exception::StoreMisaligned,
|
||||
7 => Exception::StoreFault,
|
||||
8 => Exception::UserEnvCall,
|
||||
9 => Exception::SupervisorEnvCall,
|
||||
11 => Exception::MachineEnvCall,
|
||||
12 => Exception::InstructionPageFault,
|
||||
13 => Exception::LoadPageFault,
|
||||
15 => Exception::StorePageFault,
|
||||
_ => Exception::Unknown,
|
||||
}
|
||||
}
|
||||
}
|
||||
impl Mcause {
|
||||
/// Returns the contents of the register as raw bits
|
||||
#[inline]
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
/// Returns the code field
|
||||
pub fn code(&self) -> usize {
|
||||
match () {
|
||||
#[cfg(target_pointer_width = "32")]
|
||||
() => self.bits & !(1 << 31),
|
||||
#[cfg(target_pointer_width = "64")]
|
||||
() => self.bits & !(1 << 63),
|
||||
#[cfg(target_pointer_width = "128")]
|
||||
() => self.bits & !(1 << 127),
|
||||
}
|
||||
}
|
||||
|
||||
/// Trap Cause
|
||||
#[inline]
|
||||
pub fn cause(&self) -> Trap {
|
||||
if self.is_interrupt() {
|
||||
Trap::Interrupt(Interrupt::from(self.code()))
|
||||
} else {
|
||||
Trap::Exception(Exception::from(self.code()))
|
||||
}
|
||||
}
|
||||
|
||||
/// Is trap cause an interrupt.
|
||||
#[inline]
|
||||
pub fn is_interrupt(&self) -> bool {
|
||||
match () {
|
||||
#[cfg(target_pointer_width = "32")]
|
||||
() => self.bits & (1 << 31) == 1 << 31,
|
||||
#[cfg(target_pointer_width = "64")]
|
||||
() => self.bits & (1 << 63) == 1 << 63,
|
||||
#[cfg(target_pointer_width = "128")]
|
||||
() => self.bits & (1 << 127) == 1 << 127,
|
||||
}
|
||||
}
|
||||
|
||||
/// Is trap cause an exception.
|
||||
#[inline]
|
||||
pub fn is_exception(&self) -> bool {
|
||||
!self.is_interrupt()
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Mcause {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0x342, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
Mcause { bits: r }
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
//! mcycle register
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0xB00, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
r
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
//! mcycleh register
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
match () {
|
||||
#[cfg(all(target_arch = "riscv", target_pointer_width = "32"))]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0xB80, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
r
|
||||
}
|
||||
#[cfg(any(not(target_arch = "riscv"), not(target_pointer_width = "32")))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
//! mie register
|
||||
|
||||
/// mie register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Mie {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
impl Mie {
|
||||
/// Returns the contents of the register as raw bits
|
||||
#[inline]
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
/// User Software Interrupt Enable
|
||||
#[inline]
|
||||
pub fn usoft(&self) -> bool {
|
||||
self.bits & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
/// Supervisor Software Interrupt Enable
|
||||
#[inline]
|
||||
pub fn ssoft(&self) -> bool {
|
||||
self.bits & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
/// Machine Software Interrupt Enable
|
||||
#[inline]
|
||||
pub fn msoft(&self) -> bool {
|
||||
self.bits & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
/// User Timer Interrupt Enable
|
||||
#[inline]
|
||||
pub fn utimer(&self) -> bool {
|
||||
self.bits & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
#[inline]
|
||||
pub fn stimer(&self) -> bool {
|
||||
self.bits & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
/// Machine Timer Interrupt Enable
|
||||
#[inline]
|
||||
pub fn mtimer(&self) -> bool {
|
||||
self.bits & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
/// User External Interrupt Enable
|
||||
#[inline]
|
||||
pub fn uext(&self) -> bool {
|
||||
self.bits & (1 << 8) == 1 << 8
|
||||
}
|
||||
|
||||
/// Supervisor External Interrupt Enable
|
||||
#[inline]
|
||||
pub fn sext(&self) -> bool {
|
||||
self.bits & (1 << 9) == 1 << 9
|
||||
}
|
||||
|
||||
/// Machine External Interrupt Enable
|
||||
#[inline]
|
||||
pub fn mext(&self) -> bool {
|
||||
self.bits & (1 << 11) == 1 << 11
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Mie {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0x304, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
Mie { bits: r }
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the CSR
|
||||
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))]
|
||||
#[inline]
|
||||
unsafe fn set(bits: usize) {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => asm!("csrrs x0, 0x304, $0" :: "r"(bits) :: "volatile"),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Clears the CSR
|
||||
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))]
|
||||
#[inline]
|
||||
unsafe fn clear(bits: usize) {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => asm!("csrrc x0, 0x304, $0" :: "r"(bits) :: "volatile"),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! set_csr {
|
||||
($set_field:ident, $e:expr) => {
|
||||
#[inline]
|
||||
pub unsafe fn $set_field() {
|
||||
set($e);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! clear_csr {
|
||||
($clear_field:ident, $e:expr) => {
|
||||
#[inline]
|
||||
pub unsafe fn $clear_field() {
|
||||
clear($e);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! set_clear_csr {
|
||||
($set_field:ident, $clear_field:ident, $e:expr) => {
|
||||
set_csr!($set_field, $e);
|
||||
clear_csr!($clear_field, $e);
|
||||
}
|
||||
}
|
||||
|
||||
/// User Software Interrupt Enable
|
||||
set_clear_csr!(set_usoft, clear_usoft, 1 << 0);
|
||||
/// Supervisor Software Interrupt Enable
|
||||
set_clear_csr!(set_ssoft, clear_ssoft, 1 << 1);
|
||||
/// Machine Software Interrupt Enable
|
||||
set_clear_csr!(set_msoft, clear_msoft, 1 << 3);
|
||||
/// User Timer Interrupt Enable
|
||||
set_clear_csr!(set_utimer, clear_utimer, 1 << 4);
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
set_clear_csr!(set_stimer, clear_stimer, 1 << 5);
|
||||
/// Machine Timer Interrupt Enable
|
||||
set_clear_csr!(set_mtimer, clear_mtimer, 1 << 7);
|
||||
/// User External Interrupt Enable
|
||||
set_clear_csr!(set_uext, clear_uext, 1 << 8);
|
||||
/// Supervisor External Interrupt Enable
|
||||
set_clear_csr!(set_sext, clear_sext, 1 << 9);
|
||||
/// Machine External Interrupt Enable
|
||||
set_clear_csr!(set_mext, clear_mext, 1 << 11);
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
//! minstret register
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0xB02, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
r
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
//! minstreth register
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> usize {
|
||||
match () {
|
||||
#[cfg(all(target_arch = "riscv", target_pointer_width = "32"))]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0xB82, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
r
|
||||
},
|
||||
#[cfg(any(not(target_arch = "riscv"), not(target_pointer_width = "32")))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
//! mip register
|
||||
|
||||
/// mip register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Mip {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
impl Mip {
|
||||
/// Returns the contents of the register as raw bits
|
||||
#[inline]
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
/// User Software Interrupt Pending
|
||||
#[inline]
|
||||
pub fn usoft(&self) -> bool {
|
||||
self.bits & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
/// Supervisor Software Interrupt Pending
|
||||
#[inline]
|
||||
pub fn ssoft(&self) -> bool {
|
||||
self.bits & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
/// Machine Software Interrupt Pending
|
||||
#[inline]
|
||||
pub fn msoft(&self) -> bool {
|
||||
self.bits & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
/// User Timer Interrupt Pending
|
||||
#[inline]
|
||||
pub fn utimer(&self) -> bool {
|
||||
self.bits & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
/// Supervisor Timer Interrupt Pending
|
||||
#[inline]
|
||||
pub fn stimer(&self) -> bool {
|
||||
self.bits & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
/// Machine Timer Interrupt Pending
|
||||
#[inline]
|
||||
pub fn mtimer(&self) -> bool {
|
||||
self.bits & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
/// User External Interrupt Pending
|
||||
#[inline]
|
||||
pub fn uext(&self) -> bool {
|
||||
self.bits & (1 << 8) == 1 << 8
|
||||
}
|
||||
|
||||
/// Supervisor External Interrupt Pending
|
||||
#[inline]
|
||||
pub fn sext(&self) -> bool {
|
||||
self.bits & (1 << 9) == 1 << 9
|
||||
}
|
||||
|
||||
/// Machine External Interrupt Pending
|
||||
#[inline]
|
||||
pub fn mext(&self) -> bool {
|
||||
self.bits & (1 << 11) == 1 << 11
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Mip {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0x344, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
Mip { bits: r }
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
//! misa register
|
||||
|
||||
/// misa register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Misa {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
/// Machine XLEN
|
||||
pub enum MXL {
|
||||
XLEN32,
|
||||
XLEN64,
|
||||
XLEN128,
|
||||
}
|
||||
|
||||
impl Misa {
|
||||
/// Returns the contents of the register as raw bits
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
/// Returns the machine xlen.
|
||||
pub fn mxl(&self) -> MXL {
|
||||
let value = match () {
|
||||
#[cfg(target_pointer_width = "32")]
|
||||
() => (self.bits >> 30) as u8,
|
||||
#[cfg(target_pointer_widht = "64")]
|
||||
() => (self.bits >> 62) as u8,
|
||||
};
|
||||
match value {
|
||||
1 => MXL::XLEN32,
|
||||
2 => MXL::XLEN64,
|
||||
3 => MXL::XLEN128,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Returns true when the atomic extension is implemented.
|
||||
pub fn has_extension(&self, extension: char) -> bool {
|
||||
let bit = extension as u8 - 65;
|
||||
if bit > 25 {
|
||||
return false;
|
||||
}
|
||||
self.bits & (1 >> bit) == (1 >> bit)
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Option<Misa> {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0x301, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
// When misa is hardwired to zero it means that the misa csr
|
||||
// isn't implemented.
|
||||
if r == 0 {
|
||||
None
|
||||
} else {
|
||||
Some(Misa { bits: r })
|
||||
}
|
||||
},
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
//! RISCV CSR's
|
||||
//!
|
||||
//! The following registers are not available on 64-bit implementations.
|
||||
//!
|
||||
//! - cycleh
|
||||
//! - timeh
|
||||
//! - instreth
|
||||
//! - hpmcounter[3-31]h
|
||||
//! - mcycleh
|
||||
//! - minstreth
|
||||
//! - mhpmcounter[3-31]h
|
||||
|
||||
pub mod mcause;
|
||||
pub mod mcycle;
|
||||
pub mod mcycleh;
|
||||
pub mod mie;
|
||||
pub mod mip;
|
||||
pub mod minstret;
|
||||
pub mod minstreth;
|
||||
pub mod misa;
|
||||
pub mod mstatus;
|
||||
pub mod mtvec;
|
||||
pub mod mvendorid;
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
//! mstatus register
|
||||
// TODO: Virtualization, Memory Privilege and Extension Context Fields
|
||||
|
||||
/// mstatus register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Mstatus {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
/// Machine Previous Privilege Mode
|
||||
pub enum MPP {
|
||||
Machine = 3,
|
||||
Supervisor = 1,
|
||||
User = 0,
|
||||
}
|
||||
|
||||
/// Supervisor Previous Privilege Mode
|
||||
pub enum SPP {
|
||||
Supervisor = 1,
|
||||
User = 0,
|
||||
}
|
||||
|
||||
impl Mstatus {
|
||||
/// User Interrupt Enable
|
||||
#[inline]
|
||||
pub fn uie(&self) -> bool {
|
||||
self.bits & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
/// Supervisor Interrupt Enable
|
||||
#[inline]
|
||||
pub fn sie(&self) -> bool {
|
||||
self.bits & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
/// Machine Interrupt Enable
|
||||
#[inline]
|
||||
pub fn mie(&self) -> bool {
|
||||
self.bits & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
/// User Previous Interrupt Enable
|
||||
#[inline]
|
||||
pub fn upie(&self) -> bool {
|
||||
self.bits & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
/// Supervisor Previous Interrupt Enable
|
||||
#[inline]
|
||||
pub fn spie(&self) -> bool {
|
||||
self.bits & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
/// User Previous Interrupt Enable
|
||||
#[inline]
|
||||
pub fn mpie(&self) -> bool {
|
||||
self.bits & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
/// Supervisor Previous Privilege Mode
|
||||
#[inline]
|
||||
pub fn spp(&self) -> SPP {
|
||||
match self.bits & (1 << 8) == (1 << 8) {
|
||||
true => SPP::Supervisor,
|
||||
false => SPP::User,
|
||||
}
|
||||
}
|
||||
|
||||
/// Machine Previous Privilege Mode
|
||||
#[inline]
|
||||
pub fn mpp(&self) -> MPP {
|
||||
match (self.bits & (0b11 << 11)) >> 11 {
|
||||
0b00 => MPP::User,
|
||||
0b01 => MPP::Supervisor,
|
||||
0b11 => MPP::Machine,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Mstatus {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0x300, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
Mstatus { bits: r }
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the CSR
|
||||
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))]
|
||||
#[inline]
|
||||
unsafe fn set(bits: usize) {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => asm!("csrrs x0, 0x305, $0" :: "r"(bits) :: "volatile"),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Clears the CSR
|
||||
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))]
|
||||
#[inline]
|
||||
unsafe fn clear(bits: usize) {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => asm!("csrrc x0, 0x305, $0" :: "r"(bits) :: "volatile"),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! set_csr {
|
||||
($set_field:ident, $e:expr) => {
|
||||
#[inline]
|
||||
pub unsafe fn $set_field() {
|
||||
set($e);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! clear_csr {
|
||||
($clear_field:ident, $e:expr) => {
|
||||
#[inline]
|
||||
pub unsafe fn $clear_field() {
|
||||
clear($e);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! set_clear_csr {
|
||||
($set_field:ident, $clear_field:ident, $e:expr) => {
|
||||
set_csr!($set_field, $e);
|
||||
clear_csr!($clear_field, $e);
|
||||
}
|
||||
}
|
||||
|
||||
/// User Interrupt Enable
|
||||
set_clear_csr!(set_uie, clear_uie, 1 << 0);
|
||||
/// Supervisor Interrupt Enable
|
||||
set_clear_csr!(set_sie, clear_sie, 1 << 1);
|
||||
/// Machine Interrupt Enable
|
||||
set_clear_csr!(set_mie, clear_mie, 1 << 3);
|
||||
/// User Previous Interrupt Enable
|
||||
set_csr!(set_upie, 1 << 4);
|
||||
/// Supervisor Previous Interrupt Enable
|
||||
set_csr!(set_spie, 1 << 5);
|
||||
/// Machine Previous Interrupt Enable
|
||||
set_csr!(set_mpie, 1 << 7);
|
||||
/// Supervisor Previous Privilege Mode
|
||||
#[inline]
|
||||
pub unsafe fn set_spp(spp: SPP) {
|
||||
set((spp as usize) << 8);
|
||||
}
|
||||
/// Machine Previous Privilege Mode
|
||||
#[inline]
|
||||
pub unsafe fn set_mpp(mpp: MPP) {
|
||||
set((mpp as usize) << 11);
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
//! mtvec register
|
||||
|
||||
/// mtvec register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Mtvec {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
/// Trap mode
|
||||
pub enum TrapMode {
|
||||
Direct = 0,
|
||||
Vectored = 1,
|
||||
}
|
||||
|
||||
impl Mtvec {
|
||||
/// Returns the contents of the register as raw bits
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
/// Returns the trap-vector base-address
|
||||
pub fn address(&self) -> usize {
|
||||
self.bits - (self.bits & 0b11)
|
||||
}
|
||||
|
||||
/// Returns the trap-vector mode
|
||||
pub fn trap_mode(&self) -> TrapMode {
|
||||
let mode = self.bits & 0b11;
|
||||
match mode {
|
||||
0 => TrapMode::Direct,
|
||||
1 => TrapMode::Vectored,
|
||||
_ => unimplemented!()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Mtvec {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0x305, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
Mtvec { bits: r }
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Writes the CSR
|
||||
#[cfg_attr(not(target_arch = "riscv"), allow(unused_variables))]
|
||||
#[inline]
|
||||
pub unsafe fn write(addr: usize, mode: TrapMode) {
|
||||
let bits = addr + mode as usize;
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => asm!("csrrw x0, 0x305, $0" :: "r"(bits) :: "volatile"),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
//! mvendorid register
|
||||
|
||||
/// mvendorid register
|
||||
#[derive(Clone, Copy, Debug)]
|
||||
pub struct Mvendorid {
|
||||
bits: usize,
|
||||
}
|
||||
|
||||
impl Mvendorid {
|
||||
/// Returns the contents of the register as raw bits
|
||||
pub fn bits(&self) -> usize {
|
||||
self.bits
|
||||
}
|
||||
|
||||
/// Returns the JEDEC manufacturer ID
|
||||
pub fn jedec_manufacturer(&self) -> usize {
|
||||
self.bits >> 7
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the CSR
|
||||
#[inline]
|
||||
pub fn read() -> Option<Mvendorid> {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => {
|
||||
let r: usize;
|
||||
unsafe {
|
||||
asm!("csrrs $0, 0xF11, x0" : "=r"(r) ::: "volatile");
|
||||
}
|
||||
// When mvendorid is hardwired to zero it means that the mvendorid
|
||||
// csr isn't implemented.
|
||||
if r == 0 {
|
||||
None
|
||||
} else {
|
||||
Some(Mvendorid { bits: r })
|
||||
}
|
||||
}
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => unimplemented!(),
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue