9: use `NonZeroUsize` where appropriate r=dvc94ch a=strake



Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
This commit is contained in:
bors[bot] 2018-08-19 11:12:24 +00:00
commit 591b7df808
2 changed files with 14 additions and 18 deletions

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@ -1,9 +1,11 @@
//! misa register //! misa register
use core::num::NonZeroUsize;
/// misa register /// misa register
#[derive(Clone, Copy, Debug)] #[derive(Clone, Copy, Debug)]
pub struct Misa { pub struct Misa {
bits: usize, bits: NonZeroUsize,
} }
/// Machine XLEN /// Machine XLEN
@ -16,16 +18,16 @@ pub enum MXL {
impl Misa { impl Misa {
/// Returns the contents of the register as raw bits /// Returns the contents of the register as raw bits
pub fn bits(&self) -> usize { pub fn bits(&self) -> usize {
self.bits self.bits.get()
} }
/// Returns the machine xlen. /// Returns the machine xlen.
pub fn mxl(&self) -> MXL { pub fn mxl(&self) -> MXL {
let value = match () { let value = match () {
#[cfg(target_pointer_width = "32")] #[cfg(target_pointer_width = "32")]
() => (self.bits >> 30) as u8, () => (self.bits() >> 30) as u8,
#[cfg(target_pointer_width = "64")] #[cfg(target_pointer_width = "64")]
() => (self.bits >> 62) as u8, () => (self.bits() >> 62) as u8,
}; };
match value { match value {
1 => MXL::XLEN32, 1 => MXL::XLEN32,
@ -41,7 +43,7 @@ impl Misa {
if bit > 25 { if bit > 25 {
return false; return false;
} }
self.bits & (1 >> bit) == (1 >> bit) self.bits() & (1 >> bit) == (1 >> bit)
} }
} }
@ -57,11 +59,7 @@ pub fn read() -> Option<Misa> {
} }
// When misa is hardwired to zero it means that the misa csr // When misa is hardwired to zero it means that the misa csr
// isn't implemented. // isn't implemented.
if r == 0 { NonZeroUsize::new(r).map(|bits| Misa { bits })
None
} else {
Some(Misa { bits: r })
}
}, },
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),

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@ -1,20 +1,22 @@
//! mvendorid register //! mvendorid register
use core::num::NonZeroUsize;
/// mvendorid register /// mvendorid register
#[derive(Clone, Copy, Debug)] #[derive(Clone, Copy, Debug)]
pub struct Mvendorid { pub struct Mvendorid {
bits: usize, bits: NonZeroUsize,
} }
impl Mvendorid { impl Mvendorid {
/// Returns the contents of the register as raw bits /// Returns the contents of the register as raw bits
pub fn bits(&self) -> usize { pub fn bits(&self) -> usize {
self.bits self.bits.get()
} }
/// Returns the JEDEC manufacturer ID /// Returns the JEDEC manufacturer ID
pub fn jedec_manufacturer(&self) -> usize { pub fn jedec_manufacturer(&self) -> usize {
self.bits >> 7 self.bits() >> 7
} }
} }
@ -30,11 +32,7 @@ pub fn read() -> Option<Mvendorid> {
} }
// When mvendorid is hardwired to zero it means that the mvendorid // When mvendorid is hardwired to zero it means that the mvendorid
// csr isn't implemented. // csr isn't implemented.
if r == 0 { NonZeroUsize::new(r).map(|bits| Mvendorid { bits })
None
} else {
Some(Mvendorid { bits: r })
}
} }
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))] #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
() => unimplemented!(), () => unimplemented!(),