Add mepc register.

README.md

@@ -65,7 +65,7 @@
 - [x] mtvec
 - [ ] mcounteren
 - [ ] mscratch
-- [ ] mepc
+- [x] mepc
 - [x] mcause
 - [ ] mtval
 - [x] mip

src/register/mepc.rs

@@ -0,0 +1,18 @@
+//! mepc register
+
+/// Reads the CSR
+#[inline]
+pub fn read() -> u32 {
+    match () {
+        #[cfg(target_arch = "riscv")]
+        () => {
+            let r: usize;
+            unsafe {
+                asm!("csrrs $0, 0x341, x0" : "=r"(r) ::: "volatile");
+            }
+            r as u32
+        },
+        #[cfg(not(target_arch = "riscv"))]
+        () => unimplemented!(),
+    }
+}

src/register/mod.rs

@@ -13,6 +13,7 @@
 pub mod mcause;
 pub mod mcycle;
 pub mod mcycleh;
+pub mod mepc;
 pub mod mie;
 pub mod mip;
 pub mod minstret;