21: Add 64-bit targets, reads for composite CSRs, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
This commit is contained in:
bors[bot] 2019-03-01 15:40:36 +00:00
commit 2450868523
11 changed files with 61 additions and 20 deletions

View File

@ -24,6 +24,14 @@ matrix:
rust: nightly rust: nightly
if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
- env: TARGET=riscv64imac-unknown-none-elf
rust: nightly
if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
- env: TARGET=riscv64gc-unknown-none-elf
rust: nightly
if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)
- env: TARGET=x86_64-unknown-linux-gnu - env: TARGET=x86_64-unknown-linux-gnu
rust: stable rust: stable
if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master) if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)

View File

@ -1,6 +1,6 @@
[package] [package]
name = "riscv" name = "riscv"
version = "0.4.0" version = "0.5.0"
repository = "https://github.com/rust-embedded/riscv" repository = "https://github.com/rust-embedded/riscv"
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"] authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
categories = ["embedded", "hardware-support", "no-std"] categories = ["embedded", "hardware-support", "no-std"]

View File

@ -10,7 +10,11 @@ rm -f bin/*.a
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm32.S -o bin/$crate-32.o riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm32.S -o bin/$crate-32.o
ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o bin/$crate-32.o ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o bin/$crate-32.o
cp bin/riscv32imac-unknown-none-elf.a bin/riscv32imc-unknown-none-elf.a ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o bin/$crate-32.o
riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
rm bin/$crate.o rm bin/$crate.o
rm bin/$crate-32.o rm bin/$crate-32.o

Binary file not shown.

Binary file not shown.

View File

@ -208,3 +208,25 @@ macro_rules! set_clear_csr {
clear_csr!($(#[$attr])*, $clear_field, $e); clear_csr!($(#[$attr])*, $clear_field, $e);
} }
} }
macro_rules! read_composite_csr {
($hi:expr, $lo:expr) => {
/// Reads the CSR as a 64-bit value
#[inline]
pub fn read64() -> u64 {
match () {
#[cfg(riscv32)]
() => loop {
let hi = $hi;
let lo = $lo;
if hi == $hi {
return ((hi as u64) << 32) | lo as u64;
}
},
#[cfg(not(riscv32))]
() => $lo as u64,
}
}
}
}

View File

@ -1,3 +1,4 @@
//! mcycle register //! mcycle register
read_csr_as_usize!(0xB00, __read_mcycle); read_csr_as_usize!(0xB00, __read_mcycle);
read_composite_csr!(super::mcycleh::read(), read());

View File

@ -1,5 +1,7 @@
//! mie register //! mie register
use bit_field::BitField;
/// mie register /// mie register
#[derive(Clone, Copy, Debug)] #[derive(Clone, Copy, Debug)]
pub struct Mie { pub struct Mie {
@ -16,55 +18,55 @@ impl Mie {
/// User Software Interrupt Enable /// User Software Interrupt Enable
#[inline] #[inline]
pub fn usoft(&self) -> bool { pub fn usoft(&self) -> bool {
self.bits & (1 << 0) == 1 << 0 self.bits.get_bit(0)
} }
/// Supervisor Software Interrupt Enable /// Supervisor Software Interrupt Enable
#[inline] #[inline]
pub fn ssoft(&self) -> bool { pub fn ssoft(&self) -> bool {
self.bits & (1 << 1) == 1 << 1 self.bits.get_bit(1)
} }
/// Machine Software Interrupt Enable /// Machine Software Interrupt Enable
#[inline] #[inline]
pub fn msoft(&self) -> bool { pub fn msoft(&self) -> bool {
self.bits & (1 << 3) == 1 << 3 self.bits.get_bit(3)
} }
/// User Timer Interrupt Enable /// User Timer Interrupt Enable
#[inline] #[inline]
pub fn utimer(&self) -> bool { pub fn utimer(&self) -> bool {
self.bits & (1 << 4) == 1 << 4 self.bits.get_bit(4)
} }
/// Supervisor Timer Interrupt Enable /// Supervisor Timer Interrupt Enable
#[inline] #[inline]
pub fn stimer(&self) -> bool { pub fn stimer(&self) -> bool {
self.bits & (1 << 5) == 1 << 5 self.bits.get_bit(5)
} }
/// Machine Timer Interrupt Enable /// Machine Timer Interrupt Enable
#[inline] #[inline]
pub fn mtimer(&self) -> bool { pub fn mtimer(&self) -> bool {
self.bits & (1 << 7) == 1 << 7 self.bits.get_bit(7)
} }
/// User External Interrupt Enable /// User External Interrupt Enable
#[inline] #[inline]
pub fn uext(&self) -> bool { pub fn uext(&self) -> bool {
self.bits & (1 << 8) == 1 << 8 self.bits.get_bit(8)
} }
/// Supervisor External Interrupt Enable /// Supervisor External Interrupt Enable
#[inline] #[inline]
pub fn sext(&self) -> bool { pub fn sext(&self) -> bool {
self.bits & (1 << 9) == 1 << 9 self.bits.get_bit(9)
} }
/// Machine External Interrupt Enable /// Machine External Interrupt Enable
#[inline] #[inline]
pub fn mext(&self) -> bool { pub fn mext(&self) -> bool {
self.bits & (1 << 11) == 1 << 11 self.bits.get_bit(11)
} }
} }

View File

@ -1,3 +1,4 @@
//! minstret register //! minstret register
read_csr_as_usize!(0xB02, __read_minstret); read_csr_as_usize!(0xB02, __read_minstret);
read_composite_csr!(super::minstreth::read(), read());

View File

@ -1,5 +1,7 @@
//! mip register //! mip register
use bit_field::BitField;
/// mip register /// mip register
#[derive(Clone, Copy, Debug)] #[derive(Clone, Copy, Debug)]
pub struct Mip { pub struct Mip {
@ -16,55 +18,55 @@ impl Mip {
/// User Software Interrupt Pending /// User Software Interrupt Pending
#[inline] #[inline]
pub fn usoft(&self) -> bool { pub fn usoft(&self) -> bool {
self.bits & (1 << 0) == 1 << 0 self.bits.get_bit(0)
} }
/// Supervisor Software Interrupt Pending /// Supervisor Software Interrupt Pending
#[inline] #[inline]
pub fn ssoft(&self) -> bool { pub fn ssoft(&self) -> bool {
self.bits & (1 << 1) == 1 << 1 self.bits.get_bit(1)
} }
/// Machine Software Interrupt Pending /// Machine Software Interrupt Pending
#[inline] #[inline]
pub fn msoft(&self) -> bool { pub fn msoft(&self) -> bool {
self.bits & (1 << 3) == 1 << 3 self.bits.get_bit(3)
} }
/// User Timer Interrupt Pending /// User Timer Interrupt Pending
#[inline] #[inline]
pub fn utimer(&self) -> bool { pub fn utimer(&self) -> bool {
self.bits & (1 << 4) == 1 << 4 self.bits.get_bit(4)
} }
/// Supervisor Timer Interrupt Pending /// Supervisor Timer Interrupt Pending
#[inline] #[inline]
pub fn stimer(&self) -> bool { pub fn stimer(&self) -> bool {
self.bits & (1 << 5) == 1 << 5 self.bits.get_bit(5)
} }
/// Machine Timer Interrupt Pending /// Machine Timer Interrupt Pending
#[inline] #[inline]
pub fn mtimer(&self) -> bool { pub fn mtimer(&self) -> bool {
self.bits & (1 << 7) == 1 << 7 self.bits.get_bit(7)
} }
/// User External Interrupt Pending /// User External Interrupt Pending
#[inline] #[inline]
pub fn uext(&self) -> bool { pub fn uext(&self) -> bool {
self.bits & (1 << 8) == 1 << 8 self.bits.get_bit(8)
} }
/// Supervisor External Interrupt Pending /// Supervisor External Interrupt Pending
#[inline] #[inline]
pub fn sext(&self) -> bool { pub fn sext(&self) -> bool {
self.bits & (1 << 9) == 1 << 9 self.bits.get_bit(9)
} }
/// Machine External Interrupt Pending /// Machine External Interrupt Pending
#[inline] #[inline]
pub fn mext(&self) -> bool { pub fn mext(&self) -> bool {
self.bits & (1 << 11) == 1 << 11 self.bits.get_bit(11)
} }
} }

View File

@ -1,3 +1,4 @@
//! time register //! time register
read_csr_as_usize!(0xC01, __read_time); read_csr_as_usize!(0xC01, __read_time);
read_composite_csr!(super::timeh::read(), read());