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Remove inline(always).

This commit is contained in:
David Craven 2018-03-24 19:27:00 +01:00
parent 21bfaf49ae
commit 179df42984
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GPG Key ID: 33B9E9FDE28D2C23
3 changed files with 54 additions and 54 deletions
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2
src/asm.rs
View File

@ -2,7 +2,7 @@
macro_rules! instruction { macro_rules! instruction {
($fnname:ident, $asm:expr) => ( ($fnname:ident, $asm:expr) => (
#[inline(always)] #[inline]
pub fn $fnname() { pub fn $fnname() {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(target_arch = "riscv")]

102
src/csr.rs
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@ -32,14 +32,14 @@ macro_rules! r {
} }
impl super::$TYPE { impl super::$TYPE {
#[inline(always)] #[inline]
pub fn read(&self) -> R { pub fn read(&self) -> R {
R { bits: csr_asm!(csrrs, $CSR, 0) as u32 } R { bits: csr_asm!(csrrs, $CSR, 0) as u32 }
} }
} }
impl R { impl R {
#[inline(always)] #[inline]
pub fn bits(&self) -> u32 { pub fn bits(&self) -> u32 {
self.bits self.bits
} }
@ -74,17 +74,17 @@ macro_rules! w {
} }
impl W { impl W {
#[inline(always)] #[inline]
pub fn bits(&mut self, value: u32) -> &mut W { pub fn bits(&mut self, value: u32) -> &mut W {
self.bits = value; self.bits = value;
self self
} }
#[inline(always)] #[inline]
pub fn set_bits(&mut self, value: u32) -> &mut W { pub fn set_bits(&mut self, value: u32) -> &mut W {
self.bits |= value; self.bits |= value;
self self
} }
#[inline(always)] #[inline]
pub fn clear_bits(&mut self, value: u32) -> &mut W { pub fn clear_bits(&mut self, value: u32) -> &mut W {
self.bits &= !value; self.bits &= !value;
self self
@ -280,7 +280,7 @@ impl Exception {
impl mcause::R { impl mcause::R {
#[inline(always)] #[inline]
/// Trap Cause /// Trap Cause
pub fn cause(&self) -> Trap { pub fn cause(&self) -> Trap {
let bits = self.bits(); let bits = self.bits();
@ -291,7 +291,7 @@ impl mcause::R {
} }
} }
#[inline(always)] #[inline]
/// Is trap cause an interrupt. /// Is trap cause an interrupt.
pub fn is_interrupt(&self) -> bool { pub fn is_interrupt(&self) -> bool {
match self.cause() { match self.cause() {
@ -300,7 +300,7 @@ impl mcause::R {
} }
} }
#[inline(always)] #[inline]
/// Is trap cause an exception. /// Is trap cause an exception.
pub fn is_exception(&self) -> bool { pub fn is_exception(&self) -> bool {
match self.cause() { match self.cause() {
@ -328,43 +328,43 @@ pub enum SPP {
impl mstatus::R { impl mstatus::R {
#[inline(always)] #[inline]
/// User Interrupt Enable /// User Interrupt Enable
pub fn uie(&self) -> bool { pub fn uie(&self) -> bool {
self.bits() & (1 << 0) == 1 << 0 self.bits() & (1 << 0) == 1 << 0
} }
#[inline(always)] #[inline]
/// Supervisor Interrupt Enable /// Supervisor Interrupt Enable
pub fn sie(&self) -> bool { pub fn sie(&self) -> bool {
self.bits() & (1 << 1) == 1 << 1 self.bits() & (1 << 1) == 1 << 1
} }
#[inline(always)] #[inline]
/// Machine Interrupt Enable /// Machine Interrupt Enable
pub fn mie(&self) -> bool { pub fn mie(&self) -> bool {
self.bits() & (1 << 3) == 1 << 3 self.bits() & (1 << 3) == 1 << 3
} }
#[inline(always)] #[inline]
/// User Previous Interrupt Enable /// User Previous Interrupt Enable
pub fn upie(&self) -> bool { pub fn upie(&self) -> bool {
self.bits() & (1 << 4) == 1 << 4 self.bits() & (1 << 4) == 1 << 4
} }
#[inline(always)] #[inline]
/// Supervisor Previous Interrupt Enable /// Supervisor Previous Interrupt Enable
pub fn spie(&self) -> bool { pub fn spie(&self) -> bool {
self.bits() & (1 << 5) == 1 << 5 self.bits() & (1 << 5) == 1 << 5
} }
#[inline(always)] #[inline]
/// User Previous Interrupt Enable /// User Previous Interrupt Enable
pub fn mpie(&self) -> bool { pub fn mpie(&self) -> bool {
self.bits() & (1 << 7) == 1 << 7 self.bits() & (1 << 7) == 1 << 7
} }
#[inline(always)] #[inline]
/// Supervisor Previous Privilege Mode /// Supervisor Previous Privilege Mode
pub fn spp(&self) -> SPP { pub fn spp(&self) -> SPP {
match self.bits() & (1 << 8) == (1 << 8) { match self.bits() & (1 << 8) == (1 << 8) {
@ -373,7 +373,7 @@ impl mstatus::R {
} }
} }
#[inline(always)] #[inline]
/// Machine Previous Privilege Mode /// Machine Previous Privilege Mode
pub fn mpp(&self) -> MPP { pub fn mpp(&self) -> MPP {
match (self.bits() & (0b11 << 11)) >> 11 { match (self.bits() & (0b11 << 11)) >> 11 {
@ -386,49 +386,49 @@ impl mstatus::R {
} }
impl mstatus::W { impl mstatus::W {
#[inline(always)] #[inline]
/// User Interrupt Enable /// User Interrupt Enable
pub fn uie(&mut self) -> &mut mstatus::W { pub fn uie(&mut self) -> &mut mstatus::W {
self.set_bits(1 << 0) self.set_bits(1 << 0)
} }
#[inline(always)] #[inline]
/// Supervisor Interrupt Enable /// Supervisor Interrupt Enable
pub fn sie(&mut self) -> &mut mstatus::W { pub fn sie(&mut self) -> &mut mstatus::W {
self.set_bits(1 << 1) self.set_bits(1 << 1)
} }
#[inline(always)] #[inline]
/// Machine Interrupt Enable /// Machine Interrupt Enable
pub fn mie(&mut self) -> &mut mstatus::W { pub fn mie(&mut self) -> &mut mstatus::W {
self.set_bits(1 << 3) self.set_bits(1 << 3)
} }
#[inline(always)] #[inline]
/// User Previous Interrupt Enable /// User Previous Interrupt Enable
pub fn upie(&mut self) -> &mut mstatus::W { pub fn upie(&mut self) -> &mut mstatus::W {
self.set_bits(1 << 4) self.set_bits(1 << 4)
} }
#[inline(always)] #[inline]
/// User Previous Interrupt Enable /// User Previous Interrupt Enable
pub fn spie(&mut self) -> &mut mstatus::W { pub fn spie(&mut self) -> &mut mstatus::W {
self.set_bits(1 << 5) self.set_bits(1 << 5)
} }
#[inline(always)] #[inline]
/// User Previous Interrupt Enable /// User Previous Interrupt Enable
pub fn mpie(&mut self) -> &mut mstatus::W { pub fn mpie(&mut self) -> &mut mstatus::W {
self.set_bits(1 << 7) self.set_bits(1 << 7)
} }
#[inline(always)] #[inline]
/// Supervisor Previous Privilege Mode /// Supervisor Previous Privilege Mode
pub fn spp(&mut self, value: SPP) -> &mut mstatus::W { pub fn spp(&mut self, value: SPP) -> &mut mstatus::W {
self.set_bits((value as u32) << 8) self.set_bits((value as u32) << 8)
} }
#[inline(always)] #[inline]
/// Machine Previous Privilege Mode /// Machine Previous Privilege Mode
pub fn mpp(&mut self, value: MPP) -> &mut mstatus::W { pub fn mpp(&mut self, value: MPP) -> &mut mstatus::W {
self.set_bits((value as u32) << 11) self.set_bits((value as u32) << 11)
@ -437,55 +437,55 @@ impl mstatus::W {
/// Machine Interrupt Enable CSR (mie) is ReadWrite. /// Machine Interrupt Enable CSR (mie) is ReadWrite.
impl mie::R { impl mie::R {
#[inline(always)] #[inline]
/// User Software Interrupt Enable /// User Software Interrupt Enable
pub fn usoft(&self) -> bool { pub fn usoft(&self) -> bool {
self.bits() & (1 << 0) == 1 << 0 self.bits() & (1 << 0) == 1 << 0
} }
#[inline(always)] #[inline]
/// Supervisor Software Interrupt Enable /// Supervisor Software Interrupt Enable
pub fn ssoft(&self) -> bool { pub fn ssoft(&self) -> bool {
self.bits() & (1 << 1) == 1 << 1 self.bits() & (1 << 1) == 1 << 1
} }
#[inline(always)] #[inline]
/// Machine Software Interrupt Enable /// Machine Software Interrupt Enable
pub fn msoft(&self) -> bool { pub fn msoft(&self) -> bool {
self.bits() & (1 << 3) == 1 << 3 self.bits() & (1 << 3) == 1 << 3
} }
#[inline(always)] #[inline]
/// User Timer Interrupt Enable /// User Timer Interrupt Enable
pub fn utimer(&self) -> bool { pub fn utimer(&self) -> bool {
self.bits() & (1 << 4) == 1 << 4 self.bits() & (1 << 4) == 1 << 4
} }
#[inline(always)] #[inline]
/// Supervisor Timer Interrupt Enable /// Supervisor Timer Interrupt Enable
pub fn stimer(&self) -> bool { pub fn stimer(&self) -> bool {
self.bits() & (1 << 5) == 1 << 5 self.bits() & (1 << 5) == 1 << 5
} }
#[inline(always)] #[inline]
/// Machine Timer Interrupt Enable /// Machine Timer Interrupt Enable
pub fn mtimer(&self) -> bool { pub fn mtimer(&self) -> bool {
self.bits() & (1 << 7) == 1 << 7 self.bits() & (1 << 7) == 1 << 7
} }
#[inline(always)] #[inline]
/// User External Interrupt Enable /// User External Interrupt Enable
pub fn uext(&self) -> bool { pub fn uext(&self) -> bool {
self.bits() & (1 << 8) == 1 << 8 self.bits() & (1 << 8) == 1 << 8
} }
#[inline(always)] #[inline]
/// Supervisor External Interrupt Enable /// Supervisor External Interrupt Enable
pub fn sext(&self) -> bool { pub fn sext(&self) -> bool {
self.bits() & (1 << 9) == 1 << 9 self.bits() & (1 << 9) == 1 << 9
} }
#[inline(always)] #[inline]
/// Machine External Interrupt Enable /// Machine External Interrupt Enable
pub fn mext(&self) -> bool { pub fn mext(&self) -> bool {
self.bits() & (1 << 11) == 1 << 11 self.bits() & (1 << 11) == 1 << 11
@ -493,55 +493,55 @@ impl mie::R {
} }
impl mie::W { impl mie::W {
#[inline(always)] #[inline]
/// User Software Interrupt Enable /// User Software Interrupt Enable
pub fn usoft(&mut self) -> &mut mie::W { pub fn usoft(&mut self) -> &mut mie::W {
self.set_bits(1 << 0) self.set_bits(1 << 0)
} }
#[inline(always)] #[inline]
/// Supervisor Software Interrupt Enable /// Supervisor Software Interrupt Enable
pub fn ssoft(&mut self) -> &mut mie::W { pub fn ssoft(&mut self) -> &mut mie::W {
self.set_bits(1 << 1) self.set_bits(1 << 1)
} }
#[inline(always)] #[inline]
/// Machine Software Interrupt Enable /// Machine Software Interrupt Enable
pub fn msoft(&mut self) -> &mut mie::W { pub fn msoft(&mut self) -> &mut mie::W {
self.set_bits(1 << 3) self.set_bits(1 << 3)
} }
#[inline(always)] #[inline]
/// User Timer Interrupt Enable /// User Timer Interrupt Enable
pub fn utimer(&mut self) -> &mut mie::W { pub fn utimer(&mut self) -> &mut mie::W {
self.set_bits(1 << 4) self.set_bits(1 << 4)
} }
#[inline(always)] #[inline]
/// Supervisor Timer Interrupt Enable /// Supervisor Timer Interrupt Enable
pub fn stimer(&mut self) -> &mut mie::W { pub fn stimer(&mut self) -> &mut mie::W {
self.set_bits(1 << 5) self.set_bits(1 << 5)
} }
#[inline(always)] #[inline]
/// Machine Timer Interrupt Enable /// Machine Timer Interrupt Enable
pub fn mtimer(&mut self) -> &mut mie::W { pub fn mtimer(&mut self) -> &mut mie::W {
self.set_bits(1 << 7) self.set_bits(1 << 7)
} }
#[inline(always)] #[inline]
/// User External Interrupt Enable /// User External Interrupt Enable
pub fn uext(&mut self) -> &mut mie::W { pub fn uext(&mut self) -> &mut mie::W {
self.set_bits(1 << 8) self.set_bits(1 << 8)
} }
#[inline(always)] #[inline]
/// Supervisor External Interrupt Enable /// Supervisor External Interrupt Enable
pub fn sext(&mut self) -> &mut mie::W { pub fn sext(&mut self) -> &mut mie::W {
self.set_bits(1 << 9) self.set_bits(1 << 9)
} }
#[inline(always)] #[inline]
/// Machine External Interrupt Enable /// Machine External Interrupt Enable
pub fn mext(&mut self) -> &mut mie::W { pub fn mext(&mut self) -> &mut mie::W {
self.set_bits(1 << 11) self.set_bits(1 << 11)
@ -550,55 +550,55 @@ impl mie::W {
/// Machine Interrupt Pending CSR (mip) is ReadOnly. /// Machine Interrupt Pending CSR (mip) is ReadOnly.
impl mip::R { impl mip::R {
#[inline(always)] #[inline]
/// User Software Interrupt Enable /// User Software Interrupt Enable
pub fn usoft(&self) -> bool { pub fn usoft(&self) -> bool {
self.bits() & (1 << 0) == 1 << 0 self.bits() & (1 << 0) == 1 << 0
} }
#[inline(always)] #[inline]
/// Supervisor Software Interrupt Enable /// Supervisor Software Interrupt Enable
pub fn ssoft(&self) -> bool { pub fn ssoft(&self) -> bool {
self.bits() & (1 << 1) == 1 << 1 self.bits() & (1 << 1) == 1 << 1
} }
#[inline(always)] #[inline]
/// Machine Software Interrupt Enable /// Machine Software Interrupt Enable
pub fn msoft(&self) -> bool { pub fn msoft(&self) -> bool {
self.bits() & (1 << 3) == 1 << 3 self.bits() & (1 << 3) == 1 << 3
} }
#[inline(always)] #[inline]
/// User Timer Interrupt Enable /// User Timer Interrupt Enable
pub fn utimer(&self) -> bool { pub fn utimer(&self) -> bool {
self.bits() & (1 << 4) == 1 << 4 self.bits() & (1 << 4) == 1 << 4
} }
#[inline(always)] #[inline]
/// Supervisor Timer Interrupt Enable /// Supervisor Timer Interrupt Enable
pub fn stimer(&self) -> bool { pub fn stimer(&self) -> bool {
self.bits() & (1 << 5) == 1 << 5 self.bits() & (1 << 5) == 1 << 5
} }
#[inline(always)] #[inline]
/// Machine Timer Interrupt Enable /// Machine Timer Interrupt Enable
pub fn mtimer(&self) -> bool { pub fn mtimer(&self) -> bool {
self.bits() & (1 << 7) == 1 << 7 self.bits() & (1 << 7) == 1 << 7
} }
#[inline(always)] #[inline]
/// User External Interrupt Enable /// User External Interrupt Enable
pub fn uext(&self) -> bool { pub fn uext(&self) -> bool {
self.bits() & (1 << 8) == 1 << 8 self.bits() & (1 << 8) == 1 << 8
} }
#[inline(always)] #[inline]
/// Supervisor External Interrupt Enable /// Supervisor External Interrupt Enable
pub fn sext(&self) -> bool { pub fn sext(&self) -> bool {
self.bits() & (1 << 9) == 1 << 9 self.bits() & (1 << 9) == 1 << 9
} }
#[inline(always)] #[inline]
/// Machine External Interrupt Enable /// Machine External Interrupt Enable
pub fn mext(&self) -> bool { pub fn mext(&self) -> bool {
self.bits() & (1 << 11) == 1 << 11 self.bits() & (1 << 11) == 1 << 11

4
src/interrupt.rs
View File

@ -4,7 +4,7 @@
pub use bare_metal::{CriticalSection, Mutex, Nr}; pub use bare_metal::{CriticalSection, Mutex, Nr};
/// Disables all interrupts /// Disables all interrupts
#[inline(always)] #[inline]
pub fn disable() { pub fn disable() {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(target_arch = "riscv")]
@ -19,7 +19,7 @@ pub fn disable() {
/// # Safety /// # Safety
/// ///
/// - Do not call this function inside an `interrupt::free` critical section /// - Do not call this function inside an `interrupt::free` critical section
#[inline(always)] #[inline]
pub unsafe fn enable() { pub unsafe fn enable() {
match () { match () {
#[cfg(target_arch = "riscv")] #[cfg(target_arch = "riscv")]