From 95c52341c450c7234571a85f920158fa88f52198 Mon Sep 17 00:00:00 2001
From: Gui Andrade <gh@archshift.com>
Date: Tue, 8 Oct 2019 17:56:39 -0700
Subject: [PATCH 1/2] mip: Add set/clear functions for bits

---
 src/register/mip.rs | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/src/register/mip.rs b/src/register/mip.rs
index 6633088..1a4cf82 100644
--- a/src/register/mip.rs
+++ b/src/register/mip.rs
@@ -71,3 +71,30 @@ impl Mip {
 }
 
 read_csr_as!(Mip, 0x344, __read_mip);
+set!(0x344, __set_mip);
+clear!(0x344, __clear_mip);
+
+set_clear_csr!(
+    /// User Software Interrupt Pending
+    , set_usoft, clear_usoft, 1 << 0);
+set_clear_csr!(
+    /// Supervisor Software Interrupt Pending
+    , set_ssoft, clear_ssoft, 1 << 1);
+set_clear_csr!(
+    /// Machine Software Interrupt Pending
+    , set_msoft, clear_msoft, 1 << 3);
+set_clear_csr!(
+    /// User Timer Interrupt Pending
+    , set_utimer, clear_utimer, 1 << 4);
+set_clear_csr!(
+    /// Supervisor Timer Interrupt Pending
+    , set_stimer, clear_stimer, 1 << 5);
+set_clear_csr!(
+    /// Machine Timer Interrupt Pending
+    , set_mtimer, clear_mtimer, 1 << 7);
+set_clear_csr!(
+    /// User External Interrupt Pending
+    , set_uext, clear_uext, 1 << 8);
+set_clear_csr!(
+    /// Supervisor External Interrupt Pending
+    , set_sext, clear_sext, 1 << 9);

From 7a9aa062a073dd1c69edaffee7dda84fb9917961 Mon Sep 17 00:00:00 2001
From: Gui Andrade <gh@archshift.com>
Date: Tue, 8 Oct 2019 18:10:38 -0700
Subject: [PATCH 2/2] Allow writing directly to satp register

---
 src/register/satp.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/register/satp.rs b/src/register/satp.rs
index ffd347c..d1821d3 100644
--- a/src/register/satp.rs
+++ b/src/register/satp.rs
@@ -87,7 +87,7 @@ pub enum Mode {
 }
 
 read_csr_as!(Satp, 0x180, __read_satp);
-write_csr!(0x180, __write_satp);
+write_csr_as_usize!(0x180, __write_satp);
 
 #[inline]
 #[cfg(riscv32)]