2019-12-28 18:11:12 +08:00
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# `veriscv`
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2017-09-19 22:04:12 +08:00
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2019-12-28 18:11:12 +08:00
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> Low level access to parts of the VexRiscv RISC-V processor
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2017-09-19 22:04:12 +08:00
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2020-03-18 23:36:30 +08:00
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THIS PROJECT IS NOW OBSOLETE
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2018-08-12 14:17:21 +08:00
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2020-03-18 23:36:30 +08:00
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You can access vexriscv-specific csrs in the `riscv` crate, under `riscv::registers::vexriscv::*`.
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