vexriscv-rust/Cargo.toml

16 lines
417 B
TOML
Raw Normal View History

2017-09-19 22:04:12 +08:00
[package]
name = "riscv"
2019-04-02 00:59:10 +08:00
version = "0.5.2"
2018-08-12 13:50:11 +08:00
repository = "https://github.com/rust-embedded/riscv"
2019-02-08 00:53:22 +08:00
authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
2017-09-19 22:04:12 +08:00
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISC-V processors"
2017-09-19 22:04:12 +08:00
keywords = ["riscv", "register", "peripheral"]
license = "ISC"
[dependencies]
2018-08-12 13:57:55 +08:00
bare-metal = "0.2.0"
bit_field = "0.9.0"
2018-08-12 13:56:17 +08:00
[features]
inline-asm = []