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vexriscv-rust/src/register/vmip.rs

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Fix register docs
2020-06-14 19:32:33 +08:00
//! Machine IRQ Pending register
register: add vexriscv-specific registers Vexriscv in its normal configuration has its own registers for things such as machine interrupts and system interrupts. Add wrappers for these registers. Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-08 17:22:16 +08:00
read_csr_as_usize!(0xFC0, __read_vmip);