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urukul: reorder troubleshoots

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rationale: Symptoms that appear sooner should show up earlier/have preference in the troubleshoots
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occheung
2026-01-12 14:15:47 +08:00
parent f9b0f4f1f4
commit f0c3e7c412
1 changed files with 28 additions and 28 deletions
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src/hw/urukul.md
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@@ -121,24 +121,6 @@ Press ENTER when done.
No LEDs are lit up, besides Power Good. You are suggested to reflash the gateware. See the [Building and Flashing](#building-and-flashing) sections.
### no valid window/delay
```pycon
ValueError: no valid window/delay
```
Check with the customer to see if synchronization is necessary, and disable it if it is not.
In any case, simply restart the test.
### Noise instead of signal
It may be due to misconfiguration of SUServo. Check that both firmware and pins enable/disable the SUServo mode.
### Improper frequency
This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the
customer needs, and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly.
### Urukul proto_rev mismatch
```pycon
@@ -148,16 +130,6 @@ ValueError: Urukul proto_rev mismatch
- Check the ports are connected respectively to the JSON description.
- Are you using the correct firmware?
### PLL lock timeout
```pycon
ValueError: PLL lock timeout
```
This can happen due to lack/bad clock source connection. Check that clock source is connected respective
to the customer needs, and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal
properly and `EXT`/`INT` pin matches real clocker source.
### Urukul AD9910 AUX_DAC mismatch / Urukul AD9912 product id mismatch
```pycon
@@ -172,6 +144,34 @@ ValueError: Urukul AD9912 product id mismatch
2. Ensure the Urukul is equipped with the appropriate DDS (AD9910 or AD9912).
3. Check that the SUServo pins are set up respective to the JSON description.
### no valid window/delay
```pycon
ValueError: no valid window/delay
```
Check with the customer to see if synchronization is necessary, and disable it if it is not.
In any case, simply restart the test.
### PLL lock timeout
```pycon
ValueError: PLL lock timeout
```
This can happen due to lack/bad clock source connection. Check that clock source is connected respective
to the customer needs, and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal
properly and `EXT`/`INT` pin matches real clocker source.
### Noise instead of signal
It may be due to misconfiguration of SUServo. Check that both firmware and pins enable/disable the SUServo mode.
### Improper frequency
This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the
customer needs, and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly.
### Jagged signal with 1GHz external clock on AD9910
By default, on AD9910 external clock signal is divided by 4, while it should be not divided at all with PLL disabled.