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urukul: clearly state clock division table columns as dividers

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occheung
2026-01-19 11:02:36 +08:00
committed by morgan
parent af7d5dc5f8
commit 39e2f3f3a2
1 changed files with 6 additions and 6 deletions
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src/hw/urukul.md
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@@ -63,12 +63,12 @@ OUT(((" ")))
PLL_EN -->|sysclk| OUT
```
| `clk_div` \ divider | Urukul 4410 | Urukul 4412 |
|:-------------------:|:-----------:|:-----------:|
| 0 | 4 | 1 |
| 1 | 1 | 1 |
| 2 | 2 | 2 |
| 3 | 4 | 4 |
| `clk_div` | Urukul 4410 divider | Urukul 4412 divider |
|:---------:|:-------------------:|:-------------------:|
| 0 | 4 | 1 |
| 1 | 1 | 1 |
| 2 | 2 | 2 |
| 3 | 4 | 4 |
Some important common configuration rules:
- `sysclk` is the DDS sampling clock. The typical targeted `sysclk` frequency is 1 GHz.