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separate EFC away from Shuttler

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mwojcik
2025-10-09 11:05:55 +08:00
parent 3f9d09f770
commit 01dd10c0e5
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src/SUMMARY.md
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- [Sinara 5432 DAC Zotino / Sinara 5632 DAC Fastino](./hw/zotino_fastino.md)
- [Sinara 5633 HV Amplifier](./hw/hvamp.md)
- [Sinara 5716 DAC Shuttler](./hw/shuttler.md)
- [Sinara EEM FMC Carrier (EFC)](./hw/efc.md)
- [Sinara 5518 BNC-IDC / 5528 SMA-IDC adapter](./hw/bnc_sma_idc_adapter.md)
- [Sinara 4410/4412 DDS Urukul (AD9910/AD9912)](./hw/urukul.md)
- [Sinara 5108 Sampler](./hw/sampler.md)
src/hw/efc.md
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# EFC (EEM FMC Carrier)
* [EEM FMC Carrier repo](https://github.com/sinara-hw/EEM_FMC_Carrier).
The EFC Board has an FPGA running Kasli Satellite. DRTIO communication is established through the EEM Cable.
At first power up, EFC Board and connected Kasli/Kasli-SoC calibrate the clock skews on their own EEM transceivers
and then store the values into flash memory/SD Card.
The EFC is the base for [Shuttler](./shuttler.md) and [Songbird](./songbird.md), thus JSON entry from these peripherals should be applied.
## Hardware Configurations and Connections
### EEM Cable Connection
Only the EEM0 port on the EFC board is used. The EEM Cable provides power. You can ignore the barrel jack at
the back of the board if it is placed.
### CLK Input
The EFC requires a **common** clock source with the connected device.
#### EFC v1.0
Please refer to this [issue](https://github.com/sinara-hw/EEM_FMC_Carrier/issues/44).
The clock source is controlled with an I2C IO expander.
By default, clock is taken from the MMCX input. To switch to another source, GPA2 and GPA3 of the expander must be set in firmware.
GPA2 corresponds to ``CLK_SEL1`` and GPA3 corresponds to ``CLK_SEL0``.
Thus, the firmware must be modified. In ``artiq/firmware/satman/main.rs`` find the corresponding section to set the OE and output, for example:
```rust
// Enable LEDs
io_expander.set_oe(0, 1 << 2 | 1 << 3 | 1 << 5 | 1 << 6 | 1 << 7).unwrap();
// External SMA
// For other clock settings, see the table below.
io_expander.set(0, 2, false); // CLK_SEL1 = 0
io_expander.set(0, 3, false); // CLK_SEL0 = 0
```
#### EFC v1.1+
There is a DIP switch on the board to select the clock source.
![efc_clk_sel](../img/efc_clk_sel.png)
| Clock Source | CLK_SEL0 | CLK_SEL1 |
|---|---|---|
| Front Panel SMA | 0 | 0 |
| Internal Oscillator(default) | 1 | 0 |
| MMCX | 0 | 1 |
| PE CLK | 1 | 1 |
## Building EFC Board Gateware and Firmware
The EFC Board gateware and firmware are on the [Artiq](https://github.com/m-labs/artiq) repo.
Gateware is tightly coupled, depending on the attached card, thus see [Shuttler's](./shuttler.md) and [Songbird's](./songbird.md#building-efc-firmware) building instructions.
## Routing Table configuration if EFC is connected to a Kasli Satellite
When Kasli Satellite is compiled with EFC, EFC is connected to the Satellite Repeater instance. Therefore,
you will need to specify the routing table on the Kasli/Kasli-SoC master in order to access the EFC hardware.
EFC locates at DEST 4 connecting to Repeater ID #3. The ID number goes up accordingly if more than one
EFC is connected.
Here is an example of the routing table.
You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port is connected to
Kasli Satellite(SFP0)(DEST0). EFC is connected to Kasli Satellite with DRTIO over EEM Cable (DEST4).
1. Initialize the Routing Table: `artiq_route rt.bin init`
2. Add the routing table entry for Kasli Master's Peripherals: `artiq_route rt.bin set 0 0`
3. Add the routing table entry for Kasli Satellite's Peripherals: `artiq_route rt.bin set 1 1 0`
4. Add the routing table entry for EFC: `artiq_route rt.bin set 4 1 4 0`
5. Flash the routing table on Kasli Master: `artiq_coremgmt config write -f routing_table rt.bin`
## Flashing
When you are building a crate with EFC(s), you should erase the flash/SD card config on both the EFC and
Kasli/Kasli-SoC. Always flash the EFC Board first before flashing the Kasli/Kasli-SoC.
If either of the following elements is changed, you will need to **ERASE** the stored calibrated values on both
the EFC and Kasli Master, or the communication between the boards cannot be established:
1. EEM Cable
2. Clock-Related Cable
3. EFC Board Gateware
4. Kasli/Kasli-SoC Master Gateware
5. EFC Board/Kasli/Kasli-SoC PCB
Use the Digilent HS2 JTAG adapter connected to the JTAG port on the EFC, located next to the barrel jack.
To erase the flash on the EFC board,
```shell
artiq_flash -t efc erase
```
To flash the gateware and firmware onto the EFC board, ,
```shell
artiq_flash --srcbuild -t [efc1v0, efc1v1] -d artiq_efc/EFC
```
## UART log access
UART is exposed as 4 pin header **W3** on the EFC board next to the power status LEDs. You can use an USB UART adapter such as an FTDI FT232H to connect to PC.
## Troubleshooting
### No DRTIO link
Check the logs; If DRTIO connection cannot be established, and logs are spammed, see [this](#uart-spamming-drtio-errors).
Otherwise, it could mean the common clock source is not connected.
If the symptoms still don't fit, check the routing table. You should go by these few points
- Identify the DRTIO destination of the EFC by checking the channel number in `device_db.py`. The destination is the 2 most significant hexadecimal digits of the channel. For example,
```
device_db["{efc variant}0_led0"] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x050000}
}
```
The destination is 0x5 in hexadecimal, which is 5 in decimal.
- Find the route correct DRTIO route for the EFC (see [this](https://m-labs.hk/artiq/manual/using_drtio_subkernels.html#configuring-the-routing-table)). It might be especially tricky if the EFC is connected through a Satellite (see chapter above).
### UART spamming DRTIO errors
Generally the error messages implies the data is malformed. For example, `received packet of an unknown type`.
Either wrong clock source is chosen, or the calibration for DRTIO-over-EEM is incorrect.
Verify the [clock settings](#clk-input). If they seem correct, it is likely caused by Kasli(-SoC) having an improper calibration for DRTIO-over-EEM. Consider re-doing the [flashing](#flashing) step.
src/hw/shuttler.md
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@@ -7,10 +7,6 @@ The Sinara 5716 DAC Shuttler consists of the [Shuttler](https://github.com/sinar
[Remote AFE-Board](https://github.com/sinara-hw/AFE_DAC_External), and
[EEM FMC Carrier](https://github.com/sinara-hw/EEM_FMC_Carrier) (EFC) boards.
The EFC Board has an FPGA running Kasli Satellite. DRTIO communication is established through the EEM Cable.
At first power up, EFC Board and connected Kasli/Kasli-SoC calibrate the clock skews on their own EEM transceivers
and then store the values into flash memory/SD Card.
## JSON
```json
@@ -23,6 +19,21 @@ and then store the values into flash memory/SD Card.
See how the default DRTIO destination is [generated if unspecified](https://github.com/m-labs/artiq/blob/ff1a9badfcb595d432644aea5a0b30b7478c9966/artiq/frontend/artiq_ddb_template.py#L820-L836).
For help with the EFC flashing and configuration, see the [EFC article](./efc.md)
## Building EFC firmware
To build the gateware and firmware on the release-8 branch (only supports AFE revision <= v1.2),
```shell
python -m artiq.gateware.targets.efc --hw-rev [v1.0, v1.1]
```
To build the gateware and firmware on later ARTIQ-9+ versions / the master branch,
```shell
python -m artiq.gateware.targets.efc --efc-hw-rev [v1.0, v1.1] shuttler --afe-hw-rev [v1.0, v1.1, v1.2, v1.3]
```
## Hardware Configurations and Connections
@@ -32,28 +43,6 @@ C217, C218, C213, C214 should be fitted to pass the EFC analog clock source to t
![efc_to_fmc_clk_cfg](../img/efc_to_fmc_clk_config.png)
### EEM Cable Connection
Only the EEM0 port on the EFC board is used. The EEM Cable provides power. You can ignore the barrel jack at
the back of the board if it is placed.
### CLK Input
The EFC requires a **common** clock source with the connected device.
For the EFC Board v1.0, please refer to this [issue](https://github.com/sinara-hw/EEM_FMC_Carrier/issues/44).
For the EFC Board v1.1 (or later), there is a DIP switch to select the clock source.
![efc_clk_sel](../img/efc_clk_sel.png)
| Clock Source | CLK_SEL0 | CLK_SEL1 |
|---|---|---|
| Front Panel SMA | 0 | 0 |
| Internal Oscillator(default) | 1 | 0 |
| MMCX | 0 | 1 |
| PE CLK | 1 | 1 |
### VADJ Power
The EFC Board has configurable Digital IO Voltage Level/PSU called VADJ. You should configure VADJ to 1.8V by
@@ -72,65 +61,6 @@ There is no PSU for the Remote AFE Board at this moment. For testing purposes, y
Board to a lab PSU supplying +15V, -15V, and +5V. Please make sure all voltages share a common GND and check the
pinouts carefully. Incorrect power connections can damage the Remote AFE Board.
## Building EFC Board Gateware and Firmware
The EFC Board gateware and firmware are on the [Artiq](https://github.com/m-labs/artiq) repo.
To build the gateware and firmware on the release-8 branch (only supports AFE revision <= v1.2),
```shell
python -m artiq.gateware.targets.efc --hw-rev [v1.0, v1.1]
```
To build the gateware and firmware on later ARTIQ versions / the master branch,
```shell
python -m artiq.gateware.targets.efc --efc-hw-rev [v1.0, v1.1] --afe-hw-rev [v1.0, v1.1, v1.2, v1.3]
```
## Routing Table Configuration if Shuttler is Connected to Kasli Satellite
When Kasli Satellite is compiled with Shuttler, Shuttler is connected to the Satellite Repeater instance. Therefore,
you will need to specify the routing table on the Kasli/Kasli-soc master in order to access the Shuttler hardware.
Shuttler locates at DEST 4 connecting to Repeater ID #3. The ID number goes up accordingly if more than one
Shuttler is connected.
Here provides an example to configure the routing table.
You have 1 Kasli Master and 1 Kasli Satellite. Kasli Master (SFP1)(DEST1) port is connected to
Kasli Satellite(SFP0)(DEST0). Shuttler is connected to Kasli Satellite with DRTIO over EEM Cable(DEST4).
1. Initialize the Routing Table: `artiq_route rt.bin init`
2. Add the routing table entry for Kasli Master's Peripherals: `artiq_route rt.bin set 0 0`
3. Add the routing table entry for Kasli Satellite's Peripherals: `artiq_route rt.bin set 1 1 0`
4. Add the routing table entry for Shuttler: `artiq_route rt.bin set 4 1 4 0`
5. Flash the routing table on Kasli Master: `artiq_coremgmt config write -f routing_table rt.bin`
## Flashing
When you are building a crate with shuttler(s), you should erase the flash/sd card config on both the EFC and
Kasli/Kasli-SoC. Always flash the EFC Board first before flashing the Kasli/Kasli-soc.
If either of the following elements is changed, you will need to **ERASE** the stored calibrated values on both
the EFC and Kasli Master, or the communication between the boards cannot be established:
1. EEM Cable
2. Clock-Related Cable
3. EFC Board Gateware
4. Kasli/Kasli-Soc Master Gateware
5. EFC Board/Kasli/Kasli-Soc PCB
To erase the flash on the EFC board,
```shell
artiq_flash -t efc erase
```
To flash the gateware and firmware onto the EFC board,
```shell
artiq_flash --srcbuild -t [efc1v0, efc1v1] -d artiq_efc/shuttler
```
## Testing
1. Connect the Remote AFE Card to the Shuttler
@@ -161,29 +91,7 @@ PASSED
## Troubleshooting
### UART spam error
Generally the error messages implies the data is malformed. For example, `received packet of an unknown type`.
It is likely caused by Kasli(-SoC) having an improper calibration for DRTIO-over-EEM. Consider re-do the [flashing](#flashing) step.
Check the [EFC troubleshooting guide](./efc.md#troubleshooting) for common issues.
### ADC error
Please check the AFE card revision and the [corresponding supported ARTIQ version](#building-efc-board-gateware-and-firmware).
### No DRTIO link to Shuttler
First, check [this](#uart-spam-error).
If the symptom doesn't fit, please check the routing table. You should go by these few points
- Identify the DRTIO destination of the shuttler by checking the channel number in `device_db.py`. The destination is the 2 most significant hexadecimal digits of the channel. For example,
```
device_db["shuttler0_led0"] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x050000}
}
```
The destination is 0x5 in hexadecimal, which is 5 in decimal.
- Find the route correct DRTIO route for the shuttler [(See this)](https://m-labs.hk/artiq/manual/using_drtio_subkernels.html#configuring-the-routing-table).
```