artiq-zynq/cxp_note.md

CXP

Finished

• Upconn - Low speed serial [x] Low speed serial PHY [x] 20.833Mbps & 41.666Mbps change [x] 8b10b encoder [x] TX Pipeline with priority transmission [x] Trigger [x] Trigger ack [x] Test & Ctrl packet with DMA [x] CTRL Packet serialize firmware [x] follow DRTIO DMA [x] check crc
• Downconn - GTX [x] GTX serial PHY [x] QPLL & GTX DRP to config linerate [x] Comma checker & restart rx [x] RX Pipeline with priority decoder [x] Trigger ack [x] CTRL packet DMA with extra buffer [x] Connection test sequence checker [x] CTRL Packet deserialize firmware [x] follow DRTIO DMA [x] check crc [x] GTX Multilane setup
• Camera boostrap [x] get the CXP version [x] test connection [x] discovery other extension (links) [x] set bitrate
• Camera frame pipeline [x] CXP frame packet routing (maybe no need to routing non zero streaming id (we have ROI buildin anyways)?) [x] CXP CRC32 detection

TODO

[] remove ALL debug tools [] flake.nix mod [] local_run.sh mod

Gateware

[x] rename word_dw to word_width [x] Test out CXP trigger [] add init.py for cxp?? [] Try to fix tight s/h time pins [] refactor error_cnt [] Heartbeat (is it useful?? lol) [] rename circular buffer to slots [] remove pmod/debug_sma in fns args [] add enum for gtx mode (e.g. tx only, rx only, both) [] use if tx_mode / rx_mode instead [] Region of interest engine [x] pixel gearbox [] pixel parser (xy pos) [] rtio to getting the frame

• O: trigger
• I: frame [] add a packet parser module that mux the packet?

Firmware (design with driver)

[] Camera linkdown detection [] Camera auto linkup/linkdown using threads [] API programming [] add tag handling for api calls

• support line reset in kernel using syscall [] add heartbeat checking

Coredevice Driver

[] support simple camera programming interface (Not real time)

• basic i2c-like interface with read/write u32 [] add grabber like fns & docs [] use camera test pattern black/white to verify roi https://docs.baslerweb.com/test-patterns

PR

1. push the gtx init fix
2. push the cxp core to misoc
3. push the cxp rtio core to artiq-zynq & artiq