forked from M-Labs/artiq-zynq
59 lines
2.0 KiB
Python
59 lines
2.0 KiB
Python
from migen import *
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from misoc.interconnect import stream
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from sim_pipeline import *
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from src.gateware.cxp_pipeline import *
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dut = StreamData_Generator()
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def check_case(packet=[], ack=0):
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print("=================TEST========================")
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for i, p in enumerate(packet):
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yield dut.sink.data.eq(p["data"])
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yield dut.sink.k.eq(p["k"])
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yield dut.sink.stb.eq(1)
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if "eop" in p:
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yield dut.sink.eop.eq(1)
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# CLK
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yield
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sink = dut.sink
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source = dut.source
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crc = dut.crc_inserter.crc
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print(
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# f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
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f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
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f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
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f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
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f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
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f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
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)
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# extra clk cycles
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cyc = i + 1
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for i in range(cyc, cyc + 11):
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# yield has memory for some reason
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yield dut.sink.stb.eq(0)
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yield dut.source.ack.eq(1)
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yield
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print(
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# f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
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f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
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f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
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f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
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f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
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f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
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)
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assert True
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def testbench():
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packet = [
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{"data": 0x0000_0004, "k": Replicate(0, 4)},
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{"data": 0x0000_0000, "k": Replicate(0, 4), "eop":1},
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]
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yield from check_case(packet)
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run_simulation(dut, testbench())
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