forked from M-Labs/artiq-zynq
62 lines
1.4 KiB
Rust
62 lines
1.4 KiB
Rust
#![no_std]
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#![no_main]
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#![recursion_limit="1024"] // for futures_util::select!
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extern crate alloc;
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extern crate log;
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use core::{cmp, str};
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use log::info;
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use libboard_zynq::{
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self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
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timer::GlobalTimer,
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};
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use libsupport_zynq::{logger, ram};
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mod proto;
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mod comms;
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mod pl;
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mod rtio;
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mod kernel;
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mod moninj;
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fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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let len = pl::csr::identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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pl::csr::identifier::address_write(1 + i);
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buf[i as usize] = pl::csr::identifier::data_read();
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}
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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#[no_mangle]
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pub fn main_core0() {
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let timer = GlobalTimer::start();
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let _ = logger::init();
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log::set_max_level(log::LevelFilter::Debug);
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info!("NAR3 starting...");
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const CPU_FREQ: u32 = 800_000_000;
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
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let mut ddr = zynq::ddr::DdrRam::new();
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ram::init_alloc(&mut ddr);
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info!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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}
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comms::main(timer);
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}
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