forked from M-Labs/artiq-zynq
morgan
e5036c4307
flake: download llvm11 binary instead of compiling local_run: preset cxp zc706 dev board ip addr flake: add pillow for sim libunwind build: suppress libunwind warning
35 lines
683 B
Python
35 lines
683 B
Python
from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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class test(Module):
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def __init__(self):
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self.test_cnt = Signal(32, reset=0x03020100)
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self.sync += [
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self.test_cnt[:8].eq(self.test_cnt[:8] + 4),
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self.test_cnt[8:16].eq(self.test_cnt[8:16] + 4),
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self.test_cnt[16:24].eq(self.test_cnt[16:24] + 4),
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self.test_cnt[24:].eq(self.test_cnt[24:] + 4),
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]
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dut = test()
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def packet_sim(packets=[]):
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for _ in range(0x100):
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yield
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assert True
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def testbench():
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yield from packet_sim()
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run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
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