forked from M-Labs/artiq-zynq
morgan
910bad029c
sim: add double buffer sim: add eop marker for crc checker in double buffer sim: add KCode, pak type & CRC generator sim: add Stream crossbar sim: add stream pipeline with parser & buffer sim: add frame generator & image viewer sim: add arbiter sim: add broadcaster, double buffer & eop tester sim: add roi pipeline sim: update roi
81 lines
2.5 KiB
Python
81 lines
2.5 KiB
Python
from migen import *
|
|
from misoc.interconnect.csr import *
|
|
from misoc.interconnect import stream
|
|
|
|
from sim_generator import CXPCRC32Inserter
|
|
from src.gateware.cxp_frame_pipeline import *
|
|
from src.gateware.cxp_pipeline import *
|
|
|
|
class double_buffer_pipeline(Module):
|
|
def __init__(self):
|
|
fifo = stream.SyncFIFO(word_layout_dchar, 32)
|
|
double_buffer = Double_Stream_Buffer(0x100)
|
|
dchar_dropper = DChar_Dropper()
|
|
pipeline = [fifo, double_buffer, dchar_dropper]
|
|
self.submodules += pipeline
|
|
|
|
for s, d in zip(pipeline, pipeline[1:]):
|
|
self.comb += s.source.connect(d.sink)
|
|
|
|
self.sink = pipeline[0].sink
|
|
self.source = pipeline[-1].source
|
|
|
|
# for sim, no backpressure
|
|
self.comb += self.source.ack.eq(1)
|
|
|
|
|
|
|
|
dut = double_buffer_pipeline()
|
|
|
|
|
|
def packet_sim(packets=[]):
|
|
print("=================TEST========================")
|
|
sink = dut.sink
|
|
|
|
cyc = len(packets)
|
|
pak = packets
|
|
for c in range(cyc):
|
|
yield sink.data.eq(pak[c]["data"])
|
|
yield sink.k.eq(pak[c]["k"])
|
|
yield sink.stb.eq(1)
|
|
if "eop" in pak[c]:
|
|
yield sink.eop.eq(1)
|
|
else:
|
|
yield sink.eop.eq(0)
|
|
yield
|
|
|
|
# extra clk cycles
|
|
for _ in range(cyc, cyc + 20):
|
|
yield sink.data.eq(0)
|
|
yield sink.k.eq(0)
|
|
yield sink.stb.eq(0)
|
|
yield sink.eop.eq(0)
|
|
yield
|
|
assert True
|
|
|
|
|
|
def testbench():
|
|
paks = [
|
|
{"data": C(0x7C7C7C7C, word_dw), "k": Replicate(1, 4)},
|
|
{"data": C(0x01010101, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
# {"data": C(0xF6ACEF6B, word_dw), "k": Replicate(0, 4), "eop":1},
|
|
{"data": C(0x6AEFACF6, word_dw), "k": Replicate(0, 4), "eop":1},
|
|
|
|
|
|
{"data": C(0x19191919, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x09090909, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x90909090, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
|
|
{"data": C(0xB2FD5E98, word_dw), "k": Replicate(0, 4), "eop":1},
|
|
]
|
|
yield from packet_sim(paks)
|
|
|
|
|
|
run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
|