forked from M-Labs/artiq-zynq
Denis Ovchinnikov
63594d7e3d
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC. |
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.. | ||
acpki.py | ||
analyzer.py | ||
dma.py | ||
drtio_aux_controller.py | ||
endianness.py | ||
kasli_soc.py | ||
test_dma.py | ||
zc706.py | ||
zynq_clocking.py |