1
0
Fork 0
artiq-zynq/src/gateware
Denis Ovchinnikov 63594d7e3d update configuration of IBUFDS_GTE2
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
2023-05-30 12:08:41 +08:00
..
acpki.py acpki: working 2020-09-09 21:24:49 +08:00
analyzer.py analyzer: report AXI bus errors 2020-07-20 19:51:22 +08:00
dma.py dma: report AXI bus error 2020-07-21 12:47:20 +08:00
drtio_aux_controller.py gateware: add DRTIO 2021-10-08 16:12:30 +08:00
endianness.py dma: fix endianness issues 2020-07-16 17:27:08 +08:00
kasli_soc.py update configuration of IBUFDS_GTE2 2023-05-30 12:08:41 +08:00
test_dma.py RTIO/SYS Clock merge 2023-02-17 15:52:43 +08:00
zc706.py update configuration of IBUFDS_GTE2 2023-05-30 12:08:41 +08:00
zynq_clocking.py RTIO/SYS Clock merge 2023-02-17 15:52:43 +08:00